Manisha Sharma, Hokyung Park, Yinghong Zhao, Ki-Don Lee, Liangshan Chen, J. Yoon, R. Ranjan, Caleb Dongkyan Kwon, H. Shim, M. Yeo, Shin-Young Chung, J. Haefner
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Stress polarity dependency of MOL-TDDB (Middle of Line-Time Dependent Dielectric Breakdown) is investigated on FinFET devices. Due to asymmetry in spacer dielectrics between Gate (PC) and Contact (CA), MOL-TDDB reliability can be different by bias polarity. From Vramp and TDDB evaluations, we observed MOL-TDDB reliability becomes worse when positive bias is applied to the CA side. Leakage current analysis and energy band diagram study suggested this reliability degradation can be explained by either more trap generation or more electron trapping in high-k layer (on PC side). This behavior can be suppressed by Vt-tuning capping layer.
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