J. Yun, Soon-Young Oh, H. Ji, Bin-Feng Huang, Y. Park, Seong-Hyung Park, Heui-Seung Lee, Dae-Byung Kim, Ui-Sik Kim, Han-Seob Cha, Sang Hu, Jeong‐gun Lee, H. Lee
{"title":"纳米级互补金属氧化物半导体(CMOS)用硅化镍的最佳Ni/Co厚度提取和两步快速热处理","authors":"J. Yun, Soon-Young Oh, H. Ji, Bin-Feng Huang, Y. Park, Seong-Hyung Park, Heui-Seung Lee, Dae-Byung Kim, Ui-Sik Kim, Han-Seob Cha, Sang Hu, Jeong‐gun Lee, H. Lee","doi":"10.1109/IWJT.2004.1306775","DOIUrl":null,"url":null,"abstract":"NiSi is an attractive silicide material to be applied in the nanoscale CMOSFETs. However, degradation of NiSi film after the post-silicidation annealing is one of serious demerits of NiSi. Ni/Co bi-layer is known as one of the most stable silicide structure for the improvement of the thermal stability. The formed bi-layer consists of the upper protection layer (CoSi/sub x/) and the lower conduction layer (NiSi) and their roles are different from each other. In this study, optimization of Ni/Co ratio and process condition is investigated for the nanoscale CMOSFETs.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"44 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Optimal Ni/Co thickness extraction and two step rapid thermal process of the nickel-silicide for nanoscale complementary metal oxide semiconductor (CMOS) application\",\"authors\":\"J. Yun, Soon-Young Oh, H. Ji, Bin-Feng Huang, Y. Park, Seong-Hyung Park, Heui-Seung Lee, Dae-Byung Kim, Ui-Sik Kim, Han-Seob Cha, Sang Hu, Jeong‐gun Lee, H. Lee\",\"doi\":\"10.1109/IWJT.2004.1306775\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"NiSi is an attractive silicide material to be applied in the nanoscale CMOSFETs. However, degradation of NiSi film after the post-silicidation annealing is one of serious demerits of NiSi. Ni/Co bi-layer is known as one of the most stable silicide structure for the improvement of the thermal stability. The formed bi-layer consists of the upper protection layer (CoSi/sub x/) and the lower conduction layer (NiSi) and their roles are different from each other. In this study, optimization of Ni/Co ratio and process condition is investigated for the nanoscale CMOSFETs.\",\"PeriodicalId\":342825,\"journal\":{\"name\":\"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.\",\"volume\":\"44 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-03-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWJT.2004.1306775\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWJT.2004.1306775","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Optimal Ni/Co thickness extraction and two step rapid thermal process of the nickel-silicide for nanoscale complementary metal oxide semiconductor (CMOS) application
NiSi is an attractive silicide material to be applied in the nanoscale CMOSFETs. However, degradation of NiSi film after the post-silicidation annealing is one of serious demerits of NiSi. Ni/Co bi-layer is known as one of the most stable silicide structure for the improvement of the thermal stability. The formed bi-layer consists of the upper protection layer (CoSi/sub x/) and the lower conduction layer (NiSi) and their roles are different from each other. In this study, optimization of Ni/Co ratio and process condition is investigated for the nanoscale CMOSFETs.