Area and Timing Analysis of Advanced Adders under changing Technologies

A good VLSI Design is one with low area occupancy and high speed of operation. As per Moore's law the number of transistors on a chip, increase and so does the overall chip Area. Optimizing the parameters of Area and Delay is of high importance in VLSI Design. Performance analysis and comparison of Area occupancy and Delay has been performed for 4 adders - the Ripple Carry Adder (Adder 1), the Kogge Stone Adder (Adder 2), the Carry Skip Adder (Adder 3) and the Brent Kung Adder (Adder 4), each being a 16-bit adder. The Adders were designed using Verilog code and then simulated and synthesized using RTL Encounter tool. Netlists were generated using the nclaunch tool for the three technologies. The Area and Delay results have been obtained for three technologies namely 180nm, 90nm and 45nm. At 180m, the Ripple Carry Adder occupies the least area of 1118nm2and Kogge Stone Adder has the smallest Delay of 3.495ns. At 90nm, the Ripple Carry Adder occupies the smallest Area of 315nm2 and the Kogge Stone Adder has the smallest delay of 2.957ns. The Ripple Carry Adder has a delay of 3.875ns in [3]. The reduction of delay in the paper is 10.99%.. The Carry Skip Adder has a delay of 8.106ns in [3] and a reduction of 64.16% is obtained in this paper. The Kogge Stone Adder has a delay of 6.7ns in [3]. A delay reduction of 63.65% is obtained in this paper. In [3], The Brent Kung Adder has a delay of 8.094ns. A reduction of 71.14% is obtained Amongst the four adders it has been found that the Brent Kung occupies the least Area of 123nm2 at 45nm and also has the smallest delay of 2.336 ns.