1 GHz CMOS下变频混频器

ISCE '97. Proceedings of 1997 IEEE International Symposium on Consumer Electronics (Cat. No.97TH8348) Pub Date : 1997-12-02 DOI:10.1109/ISCE.1997.658368

Seungwooi Lee, C. Yoo, Wonchan Kim, Hyun-Kyu Ryn, Wonchul Song

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引用次数: 8

摘要

介绍了一种1ghz CMOS下变频混频器。混频器采用差分结构，其中共模反馈电路通过采用鲁棒负载消除。级联级用于降低低电平到射频的馈通，测量值为-79 dB。原型混频器在标准的0.8 /spl mu/m CMOS工艺中实现，在3.3 V电源下消耗7.3 mW。功率转换增益为-0.8 dB。噪声系数为19 dB，输入IP3为0.6 dBm。

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1 GHz CMOS down-conversion mixer

A 1 GHz CMOS down-conversion mixer is described. The mixer is of differential architecture where the common-mode feedback circuit is eliminated by employing robust loads. Cascode stages are used to reduce the LO-to-RF feedthrough which is measured to be -79 dB. A prototype mixer was implemented in a standard 0.8 /spl mu/m CMOS process and consumes 7.3 mW at 3.3 V supply. The power conversion gain is -0.8 dB. The noise figure and the input IP3 are 19 dB and 0.6 dBm, respectively.

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ISCE '97. Proceedings of 1997 IEEE International Symposium on Consumer Electronics (Cat. No.97TH8348)

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