{"title":"一个3至5 ghz超宽带脉冲无线电发射机在90nm CMOS","authors":"A. Jha, R. Gharpurey, P. Kinget","doi":"10.1109/RFIC.2008.4561380","DOIUrl":null,"url":null,"abstract":"We describe a dual conversion, 3-5 GHz UWB pulse radio transmitter architecture using interleaved, IF digital-to-analog converters (DACs) followed by a partial-order hold reconstruction filters that eliminate sampling images, and an RF upconverter. 1.25 nJ is spent per pulse for a pulse-repetition rate (PRR) of 100 MHz while achieving a broadband image cancellation of 42 dBc.","PeriodicalId":253375,"journal":{"name":"2008 IEEE Radio Frequency Integrated Circuits Symposium","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"A 3 to 5-GHz UWB pulse radio transmitter in 90nm CMOS\",\"authors\":\"A. Jha, R. Gharpurey, P. Kinget\",\"doi\":\"10.1109/RFIC.2008.4561380\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We describe a dual conversion, 3-5 GHz UWB pulse radio transmitter architecture using interleaved, IF digital-to-analog converters (DACs) followed by a partial-order hold reconstruction filters that eliminate sampling images, and an RF upconverter. 1.25 nJ is spent per pulse for a pulse-repetition rate (PRR) of 100 MHz while achieving a broadband image cancellation of 42 dBc.\",\"PeriodicalId\":253375,\"journal\":{\"name\":\"2008 IEEE Radio Frequency Integrated Circuits Symposium\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-07-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 IEEE Radio Frequency Integrated Circuits Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RFIC.2008.4561380\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE Radio Frequency Integrated Circuits Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC.2008.4561380","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 3 to 5-GHz UWB pulse radio transmitter in 90nm CMOS
We describe a dual conversion, 3-5 GHz UWB pulse radio transmitter architecture using interleaved, IF digital-to-analog converters (DACs) followed by a partial-order hold reconstruction filters that eliminate sampling images, and an RF upconverter. 1.25 nJ is spent per pulse for a pulse-repetition rate (PRR) of 100 MHz while achieving a broadband image cancellation of 42 dBc.