A high-voltage compliant, electrode-invariant neural stimulator front-end in 65nm bulk-CMOS

A high-voltage compliant, 65nm bulk-CMOS neural stimulator front-end is presented which can interface with a wide range of electrode impedances. With bulk-CMOS compatibility, the presented design can be easily integrated on the same silicon chip with other blocks needed for implantable bidirectional neural interfaces (e.g. high-density neural recording, DSP, memory, wireless interfaces). Measurements show voltage compliance exceeding +/-10V (with 1V and 2.5V devices) when driving 50μA to 2mA biphasic stimulus through resistive and capacitive electrode models. In vivo measurement results are provided (anesthetized rat) which demonstrate the efficacy of the integrated stimulator in bidirectional neural interface applications. The stimulator front-end active die area is 2mm2. While delivering 2mA, 200μs pulse-width biphasic stimulus at 300Hz the chip consumes 9.33mW; stand-by power consumption is approximately 300μW.