Joseph J. Bouchez, Tuong Nguyen, V. Zomorrodian, E. Reese, D. Sturzebecher
{"title":"基于新型输入拓扑的2-5GHz 100W连续波MMIC限制器","authors":"Joseph J. Bouchez, Tuong Nguyen, V. Zomorrodian, E. Reese, D. Sturzebecher","doi":"10.1109/CSICS.2013.6659191","DOIUrl":null,"url":null,"abstract":"A CW 100W MMIC limiter covering 2-5GHz band is presented using TriQuint's 2MI GaAs VPIN process. The new architecture uses a binary power splitter topology to distribute the input power equally to all the input anti-parallel diodes, resulting in higher input power handling capability. The limiter is able to withstand more than 100W of input power with flat leakage less than 16 dBm. The insertion loss is less than 0.5 dB. The input and output return loss is greater than 15 dB. Performance degradation was negligible after a 1 hour test with 100W CW input power.","PeriodicalId":257256,"journal":{"name":"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"A 2-5GHz 100W CW MMIC Limiter Using a Novel Input Topology\",\"authors\":\"Joseph J. Bouchez, Tuong Nguyen, V. Zomorrodian, E. Reese, D. Sturzebecher\",\"doi\":\"10.1109/CSICS.2013.6659191\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A CW 100W MMIC limiter covering 2-5GHz band is presented using TriQuint's 2MI GaAs VPIN process. The new architecture uses a binary power splitter topology to distribute the input power equally to all the input anti-parallel diodes, resulting in higher input power handling capability. The limiter is able to withstand more than 100W of input power with flat leakage less than 16 dBm. The insertion loss is less than 0.5 dB. The input and output return loss is greater than 15 dB. Performance degradation was negligible after a 1 hour test with 100W CW input power.\",\"PeriodicalId\":257256,\"journal\":{\"name\":\"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-11-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CSICS.2013.6659191\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSICS.2013.6659191","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 2-5GHz 100W CW MMIC Limiter Using a Novel Input Topology
A CW 100W MMIC limiter covering 2-5GHz band is presented using TriQuint's 2MI GaAs VPIN process. The new architecture uses a binary power splitter topology to distribute the input power equally to all the input anti-parallel diodes, resulting in higher input power handling capability. The limiter is able to withstand more than 100W of input power with flat leakage less than 16 dBm. The insertion loss is less than 0.5 dB. The input and output return loss is greater than 15 dB. Performance degradation was negligible after a 1 hour test with 100W CW input power.