Effectiveness of stuck-at test sets to detect bridging faults in Iddq environment

Recently, it has been recognized that logic testing is very inefficient to detect physical defects in CMOS circuits. Most of the physical defects are modeled as bridging and open faults, which are not detected using a stuck-at fault model. In this study, we examined the detect efficiency of stuck-at test sets for bridging faults in Iddq environment. Our stuck-at test vectors are generated by standard ATPG programs. These test vectors are applied while power supply current is monitored. A high current state in the circuit is considered as a presence of a fault. Sets of combinational and sequential circuits are used in this study. The results are given in terms of intra-transistor and gate-level bridging fault coverages.<>