Double edge-triggered half-static clock-gated D-type flip-flop

This paper proposes a double edge-triggered half-static clock-gated D-type flip-flop (DHSCGFF), which consists of two parallel dynamic master latches connected in parallel and a single half-static latch with clock-gating circuit. The proposed DHSCGFF makes use of a clock-gating circuit to achieve better race tolerance, circuit compactness and energy efficiency without the use of pulse generator. Simulation results of the proposed circuit using a 0.18 µm technology is presented. Results indicate that the proposed circuit can achieve a 4 Gbits/sec data rate and a 96% redundant power reduction.