{"title":"恒环路带宽LC-VCO锁相环频率合成器","authors":"J. Huang, L. Yang, Shou-hui Xu","doi":"10.1109/ICCPS.2016.7751122","DOIUrl":null,"url":null,"abstract":"This paper precented a phase-locked loop frequency synthesizer with almost constant loop bandwidth. In order to reduce the loop bandwidth variations caused by the LC-VCO gain, a calibration system is introduced, which sets the charge-pump current to be inversely proportional to the square of the divider ratio. The frequency synthesizer with this technique was fabricated in 0.13μm CMOS process. The measured results show that this method keeps the loop bandwidth almost a constant in frequency range of 2.44G~2.8GHz while consuming less power with better in-band phase noise.","PeriodicalId":348961,"journal":{"name":"2016 International Conference On Communication Problem-Solving (ICCP)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"The LC-VCO PLL frequency synthesizers with constant loop bandwidth\",\"authors\":\"J. Huang, L. Yang, Shou-hui Xu\",\"doi\":\"10.1109/ICCPS.2016.7751122\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper precented a phase-locked loop frequency synthesizer with almost constant loop bandwidth. In order to reduce the loop bandwidth variations caused by the LC-VCO gain, a calibration system is introduced, which sets the charge-pump current to be inversely proportional to the square of the divider ratio. The frequency synthesizer with this technique was fabricated in 0.13μm CMOS process. The measured results show that this method keeps the loop bandwidth almost a constant in frequency range of 2.44G~2.8GHz while consuming less power with better in-band phase noise.\",\"PeriodicalId\":348961,\"journal\":{\"name\":\"2016 International Conference On Communication Problem-Solving (ICCP)\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 International Conference On Communication Problem-Solving (ICCP)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCPS.2016.7751122\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 International Conference On Communication Problem-Solving (ICCP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCPS.2016.7751122","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The LC-VCO PLL frequency synthesizers with constant loop bandwidth
This paper precented a phase-locked loop frequency synthesizer with almost constant loop bandwidth. In order to reduce the loop bandwidth variations caused by the LC-VCO gain, a calibration system is introduced, which sets the charge-pump current to be inversely proportional to the square of the divider ratio. The frequency synthesizer with this technique was fabricated in 0.13μm CMOS process. The measured results show that this method keeps the loop bandwidth almost a constant in frequency range of 2.44G~2.8GHz while consuming less power with better in-band phase noise.