{"title":"一种带隙参考电路的设计方法","authors":"J. Kaur, R. Kaushik, A. Srivastava, Sakshi Singh","doi":"10.1109/ICSPVCE46182.2019.9092822","DOIUrl":null,"url":null,"abstract":"The paper presents a systematic approach of designing a bandgap reference circuit using 2-stage operational amplifier. The circuit is designed using 0.18 µm CMOS process. In simulation we achieve a reference of 789 mV with a coefficient of temperature 71.69 ppm/ºC for the temperature range 104°C at 1.8 V supply voltage. The reference voltage circuit consumed 60.82 µW of power. The layout with DRC and LVS check of the BGR core was completed. The overall area of the designed BGR circuit is 0.027 mm2.","PeriodicalId":335856,"journal":{"name":"2019 1st International Conference on Signal Processing, VLSI and Communication Engineering (ICSPVCE)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A Design Approach for Bandgap Reference Circuit\",\"authors\":\"J. Kaur, R. Kaushik, A. Srivastava, Sakshi Singh\",\"doi\":\"10.1109/ICSPVCE46182.2019.9092822\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper presents a systematic approach of designing a bandgap reference circuit using 2-stage operational amplifier. The circuit is designed using 0.18 µm CMOS process. In simulation we achieve a reference of 789 mV with a coefficient of temperature 71.69 ppm/ºC for the temperature range 104°C at 1.8 V supply voltage. The reference voltage circuit consumed 60.82 µW of power. The layout with DRC and LVS check of the BGR core was completed. The overall area of the designed BGR circuit is 0.027 mm2.\",\"PeriodicalId\":335856,\"journal\":{\"name\":\"2019 1st International Conference on Signal Processing, VLSI and Communication Engineering (ICSPVCE)\",\"volume\":\"58 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 1st International Conference on Signal Processing, VLSI and Communication Engineering (ICSPVCE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSPVCE46182.2019.9092822\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 1st International Conference on Signal Processing, VLSI and Communication Engineering (ICSPVCE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSPVCE46182.2019.9092822","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The paper presents a systematic approach of designing a bandgap reference circuit using 2-stage operational amplifier. The circuit is designed using 0.18 µm CMOS process. In simulation we achieve a reference of 789 mV with a coefficient of temperature 71.69 ppm/ºC for the temperature range 104°C at 1.8 V supply voltage. The reference voltage circuit consumed 60.82 µW of power. The layout with DRC and LVS check of the BGR core was completed. The overall area of the designed BGR circuit is 0.027 mm2.