加速硬件仿真:测试台架代码仿真

I. Mavroidis, I. Papaefstathiou
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引用次数: 11

摘要

今天的等离子体验证挑战需要高性能的仿真解决方案,例如硬件仿真加速器和模拟器,它们已经在硬件和电子系统设计中心中使用了大约十年。特别是为了加速功能仿真,采用了硬件仿真,从而将计算密集型的任务从软件模拟器中卸载出来。然而,软件模拟器和硬件模拟器之间的通信开销成为一个新的关键瓶颈。在我们的工作中,我们引入了一种在软件和硬件之间重新划分仿真的新方法,以最大限度地减少这种通信瓶颈。使用本文中描述的技术,我们能够将传统上由软件模拟器完成的大部分工作卸载到硬件模拟器上。我们使用实际设计的实验表明,所提出的方法显著降低了通信开销,并且比传统的硬件仿真系统性能高出7倍以上。最后,我们提供了一种在测试运行时观察和修改硬件仿真器内部状态的方法。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Accelerating hardware simulation: Testbench code emulation
Todaypsilas verification challenges require high-performance simulation solutions, such as hardware simulation accelerators and emulators, that have been in use in hardware and electronic system design centers for approximately the last decade. In particular, in order to accelerate functional simulation, hardware emulation is used so as to offload calculation-intensive tasks from the software simulator. However, the communication overhead between the software simulator and the hardware emulator is becoming a new critical bottleneck. In our work we introduce a novel way of repartitioning the simulation between software and hardware in order to minimize this communication bottleneck. Using the techniques described in this paper we are able to offload a big part of the work that is traditionally done by the software simulator, onto the hardware emulator. Our experiments, using real-world designs, demonstrate that the proposed method reduces significantly the communication overhead and outperforms the conventional hardware emulation systems by a factor of more than 7. Finally, we provide a way of observing and modifying the internal state of the hardware emulator while the test is running.
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