{"title":"采用可复位延迟线的无谐波快速锁相环","authors":"Kai Huang, Zhikuang Cai, Jun Yang","doi":"10.1109/ICCRD.2010.176","DOIUrl":null,"url":null,"abstract":"An all digital delay-locked loop (ADDLL) with \"reset in every step\" (RES) delay line is developed in order to reduce the locking time. Due to the novel resettable mechanism of delay line, the DLL has the property of fast-locking and harmonic-free. The locking time can be reduced to N+1, where N is the bits' number of the control code for a delay line. According to the simulation result in SMIC 180nm CMOS technology, the proposed delay-locked loop (DLL) can cover the operating range from 50 to 250MHz.","PeriodicalId":158568,"journal":{"name":"2010 Second International Conference on Computer Research and Development","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A Harmonic-Free and Fast-Locking Delay-Locked Loop Adopting a Resettable Delay Line\",\"authors\":\"Kai Huang, Zhikuang Cai, Jun Yang\",\"doi\":\"10.1109/ICCRD.2010.176\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An all digital delay-locked loop (ADDLL) with \\\"reset in every step\\\" (RES) delay line is developed in order to reduce the locking time. Due to the novel resettable mechanism of delay line, the DLL has the property of fast-locking and harmonic-free. The locking time can be reduced to N+1, where N is the bits' number of the control code for a delay line. According to the simulation result in SMIC 180nm CMOS technology, the proposed delay-locked loop (DLL) can cover the operating range from 50 to 250MHz.\",\"PeriodicalId\":158568,\"journal\":{\"name\":\"2010 Second International Conference on Computer Research and Development\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-05-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 Second International Conference on Computer Research and Development\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCRD.2010.176\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 Second International Conference on Computer Research and Development","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCRD.2010.176","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Harmonic-Free and Fast-Locking Delay-Locked Loop Adopting a Resettable Delay Line
An all digital delay-locked loop (ADDLL) with "reset in every step" (RES) delay line is developed in order to reduce the locking time. Due to the novel resettable mechanism of delay line, the DLL has the property of fast-locking and harmonic-free. The locking time can be reduced to N+1, where N is the bits' number of the control code for a delay line. According to the simulation result in SMIC 180nm CMOS technology, the proposed delay-locked loop (DLL) can cover the operating range from 50 to 250MHz.
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