将系统规格转换为VHDL

Proceedings of the European Conference on Design Automation. Pub Date : 1991-02-25 DOI:10.1109/EDAC.1991.206432

Sanjiv Narayan, F. Vahid, D. Gajski

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引用次数: 38

摘要

基于分层和并发状态图的语言在指定系统级设计方面功能强大。模拟这些语言可以通过翻译成模拟语言(如VHDL)，然后使用可用的模拟器来简化。本文描述了规范语言中常见的系统级抽象，并给出了保持语义的VHDL实现。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Translating system specifications to VHDL

Languages based on hierarchical and concurrent state diagrams are powerful in specifying system level designs. Simulating such languages can be simplified by translating to a simulation language such as VHDL and then using available simulators. This paper describes system level abstractions commonly found in specification languages and presents semantic preserving VHDL implementations.<>

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来源期刊

Proceedings of the European Conference on Design Automation.

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