{"title":"不同偏置条件下栅极全能叠加纳米片差分放大器的设计","authors":"J. Sousa, W. Perina, J. Martino, P. Agopian","doi":"10.1109/SBMicro50945.2021.9585744","DOIUrl":null,"url":null,"abstract":"This paper presents the DC design of a differential amplifier, an important building block on analog and mixed signal designs, utilizing the Verilog-A approach on Gate-All-Around Nanosheet (GAA-NSH) devices. The GAA-NSH is a device with two stacked silicon sheets in which the gate fully surrounds the channel, presenting the best electrostatic coupling possible for MOS technologies. The device has a 104nm effective width while having a physical width of only 15nm. The differential amplifier was designed with a VDD of 2.1V and input common mode of 1.4V, while biased in different inversion regions with gm/ID values of 5 V-1, 8 V-1 and 11 V-1. The gm/ID = 8V-1 project was compared against a FinFET differential amplifier project, showing an improvement of gain and transconductance while occupying less physical area. Higher efficiency projects (gm/ID= 11 V-1) present a higher gain while decreasing current consumption.","PeriodicalId":318195,"journal":{"name":"2021 35th Symposium on Microelectronics Technology and Devices (SBMicro)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of a Gate-All-Around Stacked Nanosheet Differential Amplifier under Different Bias Conditions\",\"authors\":\"J. Sousa, W. Perina, J. Martino, P. Agopian\",\"doi\":\"10.1109/SBMicro50945.2021.9585744\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the DC design of a differential amplifier, an important building block on analog and mixed signal designs, utilizing the Verilog-A approach on Gate-All-Around Nanosheet (GAA-NSH) devices. The GAA-NSH is a device with two stacked silicon sheets in which the gate fully surrounds the channel, presenting the best electrostatic coupling possible for MOS technologies. The device has a 104nm effective width while having a physical width of only 15nm. The differential amplifier was designed with a VDD of 2.1V and input common mode of 1.4V, while biased in different inversion regions with gm/ID values of 5 V-1, 8 V-1 and 11 V-1. The gm/ID = 8V-1 project was compared against a FinFET differential amplifier project, showing an improvement of gain and transconductance while occupying less physical area. Higher efficiency projects (gm/ID= 11 V-1) present a higher gain while decreasing current consumption.\",\"PeriodicalId\":318195,\"journal\":{\"name\":\"2021 35th Symposium on Microelectronics Technology and Devices (SBMicro)\",\"volume\":\"67 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-08-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 35th Symposium on Microelectronics Technology and Devices (SBMicro)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SBMicro50945.2021.9585744\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 35th Symposium on Microelectronics Technology and Devices (SBMicro)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SBMicro50945.2021.9585744","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of a Gate-All-Around Stacked Nanosheet Differential Amplifier under Different Bias Conditions
This paper presents the DC design of a differential amplifier, an important building block on analog and mixed signal designs, utilizing the Verilog-A approach on Gate-All-Around Nanosheet (GAA-NSH) devices. The GAA-NSH is a device with two stacked silicon sheets in which the gate fully surrounds the channel, presenting the best electrostatic coupling possible for MOS technologies. The device has a 104nm effective width while having a physical width of only 15nm. The differential amplifier was designed with a VDD of 2.1V and input common mode of 1.4V, while biased in different inversion regions with gm/ID values of 5 V-1, 8 V-1 and 11 V-1. The gm/ID = 8V-1 project was compared against a FinFET differential amplifier project, showing an improvement of gain and transconductance while occupying less physical area. Higher efficiency projects (gm/ID= 11 V-1) present a higher gain while decreasing current consumption.