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引用次数: 3
摘要
本文设计了一种基于小电流二阶差分放大器结构的RFID低功耗解调器。该解调器是一个学术项目，根据标准的0.5 μ m n阱CMOS工艺设计规则进行了设计。解调器电源将在电压倍增器的帮助下从射频能量中获取。仿真结果表明，该系统的静态功耗为2.5 μ w，动态功耗约为0.21 μ w。该解调器占地面积为243 μ m × 95.5 μ m，其中无源元件占等效面积的74.96%
A Low-Power 2.7μW, 915-MHz Demodulator for RFID Applications
This paper presents the design of a low-power demodulator for RFID applications based on a low-current twice differential amplifier structure. The demodulator, which is an academic project, has been designed according to the technological design rules of a standard 0.5 mum, N-well CMOS process. The demodulator power supply would be taken from the RF energy with help of a voltage multiplier. From simulations results a static power consumption of 2.5 muW was deduced whereas the dynamic one was approximately 0.21 muW. The demodulator occupies an area of 243 mumtimes95.5 mum from which passive components cover an equivalent area of 74.96%
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