{"title":"自定义VLIW架构的设计空间探索:使用VEX编译器直接设置照片打印机硬件","authors":"D. Saptono, V. Brost, Fan Yang, E. Prasetyo","doi":"10.1109/SITIS.2008.69","DOIUrl":null,"url":null,"abstract":"Increasingly more computing power is demanded for contemporary applications such as multimedia, 3D visualization, and telecommunication. This paper presents a design space exploration (DSE) experience for an embedded VLIW processor that allows finding out the best architecture for given application. The proposed method has been implemented and tested using an image processing chain for direct photo printer. Our results show a considerable improvement in hardware cost and performance. After the best architecture is identified, we applied a technique to optimize the code in VEX system that uses ¿inlining¿ function in order to reduce execution time.","PeriodicalId":202698,"journal":{"name":"2008 IEEE International Conference on Signal Image Technology and Internet Based Systems","volume":"255 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-11-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"Design Space Exploration for a Custom VLIW Architecture: Direct Photo Printer Hardware Setting Using VEX Compiler\",\"authors\":\"D. Saptono, V. Brost, Fan Yang, E. Prasetyo\",\"doi\":\"10.1109/SITIS.2008.69\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Increasingly more computing power is demanded for contemporary applications such as multimedia, 3D visualization, and telecommunication. This paper presents a design space exploration (DSE) experience for an embedded VLIW processor that allows finding out the best architecture for given application. The proposed method has been implemented and tested using an image processing chain for direct photo printer. Our results show a considerable improvement in hardware cost and performance. After the best architecture is identified, we applied a technique to optimize the code in VEX system that uses ¿inlining¿ function in order to reduce execution time.\",\"PeriodicalId\":202698,\"journal\":{\"name\":\"2008 IEEE International Conference on Signal Image Technology and Internet Based Systems\",\"volume\":\"255 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-11-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 IEEE International Conference on Signal Image Technology and Internet Based Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SITIS.2008.69\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE International Conference on Signal Image Technology and Internet Based Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SITIS.2008.69","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design Space Exploration for a Custom VLIW Architecture: Direct Photo Printer Hardware Setting Using VEX Compiler
Increasingly more computing power is demanded for contemporary applications such as multimedia, 3D visualization, and telecommunication. This paper presents a design space exploration (DSE) experience for an embedded VLIW processor that allows finding out the best architecture for given application. The proposed method has been implemented and tested using an image processing chain for direct photo printer. Our results show a considerable improvement in hardware cost and performance. After the best architecture is identified, we applied a technique to optimize the code in VEX system that uses ¿inlining¿ function in order to reduce execution time.