混合门阵列与定制集成电路设计方法的比较

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1984.1156631

C. Erdelyi, R. Bechade, M. Concannon, W. Hoffman

{"title":"混合门阵列与定制集成电路设计方法的比较","authors":"C. Erdelyi, R. Bechade, M. Concannon, W. Hoffman","doi":"10.1109/ISSCC.1984.1156631","DOIUrl":null,"url":null,"abstract":"This paper will present a comparison of gate-array, mixed gate-array-custom and full custom implementations of a 32b NMOS microprocessor. Use of 5V and 3.4V on-chip supply voltages and automated gate-array design for parts of the chip has resulted in a speed and power dissipation of 230ns/2.8W, comparable to the full-custom approach (170ns/3W) in half the design time.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A comparison of mixed gate array and custom IC design methods\",\"authors\":\"C. Erdelyi, R. Bechade, M. Concannon, W. Hoffman\",\"doi\":\"10.1109/ISSCC.1984.1156631\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper will present a comparison of gate-array, mixed gate-array-custom and full custom implementations of a 32b NMOS microprocessor. Use of 5V and 3.4V on-chip supply voltages and automated gate-array design for parts of the chip has resulted in a speed and power dissipation of 230ns/2.8W, comparable to the full-custom approach (170ns/3W) in half the design time.\",\"PeriodicalId\":260117,\"journal\":{\"name\":\"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1984.1156631\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1984.1156631","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

摘要

本文将比较32b NMOS微处理器的门阵列、混合门阵列自定义和完全自定义实现。采用5V和3.4V片上电源电压和芯片部分的自动门阵列设计，速度和功耗为230ns/2.8W，与全定制方法(170ns/3W)相比，设计时间缩短了一半。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A comparison of mixed gate array and custom IC design methods

This paper will present a comparison of gate-array, mixed gate-array-custom and full custom implementations of a 32b NMOS microprocessor. Use of 5V and 3.4V on-chip supply voltages and automated gate-array design for parts of the chip has resulted in a speed and power dissipation of 230ns/2.8W, comparable to the full-custom approach (170ns/3W) in half the design time.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

自引率

0.00%

发文量