Clock domain crossing (CDC) for inter-logic-layer communication in 3-D ICs

3D technology is becoming more popular due to improved design density and performance. However, single global clock distribution to a complex system, like 3-D IC, is a very challenging task. Due to potentially heterogeneous, dice integration also omens for increasing environmental and process non-idealities. Therefore, inter-logic layer communication in 3-D ICs can leverage from clock domain crossing (CDC) techniques to perform timely and correct data transactions. In this paper, we investigate two classes of CDC techniques, the pseudo quasi-delay insensitive (QDI) based GALS and loosely synchronous CDC technique under 3-D IC context. It is found that although pseudo QDI based GALS design provides an attractive solution because of the relaxed constraint on clock distribution network, but for 8 or higher data-bits/transaction its hardware overhead becomes more than the loosely synchronous design. To the best of authors' knowledge this is a premier work in investigating design guidelines for CDC techniques in through silicon via (TSV) based 3-D ICs.