用于改进短通道控制的翅片宽度缩放，以及积极缩放通道长度SOI finfet的性能

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2013-10-01 DOI:10.1109/S3S.2013.6716521

A. Paul, C. Yeh, T. Standaert, Jeffrey B. Johnson, A. Bryant, N. Tripathi, G. Tsutsui, T. Yamashita, V. Basker, J. Faltermeier, Jin Cho, H. Bu, M. Khare

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引用次数: 1

摘要

这项工作提出了鳍宽(Dfin)缩放到15nm以下的SOI finfet。该工艺流程提供了由DIBL和亚阈值摆动(SS)的通用静电缩放所描述的稳健的Dfin缩放。对于20nm沟道长度的n/ pfinfet，高场长沟道迁移率下降了6%，而DIBL和SS分别提高了1.5倍和2倍。采用Dfin标度后，p finet和n finet的有效电流(Ieff)分别提高了~20%和~30%。

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Fin width scaling for improved short channel control and performance in aggressively scaled channel length SOI finFETs

This work presents SOI finFETs with fin width (Dfin) scaled to sub 15nm. The process flow provides robust Dfin scaling as depicted by the universal electrostatic scaling of the DIBL and sub-threshold swing (SS). The high field long channel mobility drops by ~6% with Dfin scaling, however, DIBL and SS improves by ~1.5X and ~2X, respectively, for 20nm channel length n/pfinFETs. The effective current (Ieff) at fixed Ioff improves by ~20% and ~30% for p and n finFETs, respectively, with Dfin scaling.

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2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

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