{"title":"硅厚度对传统无结场效应晶体管性能的影响","authors":"M. Agarwal, V. Narula","doi":"10.1063/5.0016988","DOIUrl":null,"url":null,"abstract":"The performance of N-type double gate junctionless Field Effect Transistor(JLFET) at different silicon thickness is studied using TCAD simulations. The performance of the device is highly dependent on silicon thickness. The different parameters like ON current, OFF current, ON/OFF current ratio, Subthreshold Slope(SS) and threshold Voltage has been studied at different silicon thickness varied from 6nm to 12nm. It is observed from the simulations that with the increase in silicon thickness the device performance has degraded. The best performance parameters are obtained when the silicon thickness is 6nm. This paper also demonstrates the correlation between the gate work function and the silicon thickness for better device performance. Further, an improvement in the performance parameters even on increasing the silicon thickness has been observed on increasing the work function of the gate material.","PeriodicalId":222119,"journal":{"name":"DAE SOLID STATE PHYSICS SYMPOSIUM 2019","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Effect of silicon thickness on the performance of conventional junctionless field effect transistor\",\"authors\":\"M. Agarwal, V. Narula\",\"doi\":\"10.1063/5.0016988\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The performance of N-type double gate junctionless Field Effect Transistor(JLFET) at different silicon thickness is studied using TCAD simulations. The performance of the device is highly dependent on silicon thickness. The different parameters like ON current, OFF current, ON/OFF current ratio, Subthreshold Slope(SS) and threshold Voltage has been studied at different silicon thickness varied from 6nm to 12nm. It is observed from the simulations that with the increase in silicon thickness the device performance has degraded. The best performance parameters are obtained when the silicon thickness is 6nm. This paper also demonstrates the correlation between the gate work function and the silicon thickness for better device performance. Further, an improvement in the performance parameters even on increasing the silicon thickness has been observed on increasing the work function of the gate material.\",\"PeriodicalId\":222119,\"journal\":{\"name\":\"DAE SOLID STATE PHYSICS SYMPOSIUM 2019\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-11-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"DAE SOLID STATE PHYSICS SYMPOSIUM 2019\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1063/5.0016988\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"DAE SOLID STATE PHYSICS SYMPOSIUM 2019","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1063/5.0016988","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Effect of silicon thickness on the performance of conventional junctionless field effect transistor
The performance of N-type double gate junctionless Field Effect Transistor(JLFET) at different silicon thickness is studied using TCAD simulations. The performance of the device is highly dependent on silicon thickness. The different parameters like ON current, OFF current, ON/OFF current ratio, Subthreshold Slope(SS) and threshold Voltage has been studied at different silicon thickness varied from 6nm to 12nm. It is observed from the simulations that with the increase in silicon thickness the device performance has degraded. The best performance parameters are obtained when the silicon thickness is 6nm. This paper also demonstrates the correlation between the gate work function and the silicon thickness for better device performance. Further, an improvement in the performance parameters even on increasing the silicon thickness has been observed on increasing the work function of the gate material.