减小耦合电容，采用电容-晶体管耦合电路

2015 9th International Conference on Electrical and Electronics Engineering (ELECO) Pub Date : 2015-11-01 DOI:10.1109/ELECO.2015.7394649

Majid Eslami Farsani, Noushin Ghaderi

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引用次数: 3

摘要

本文提出了一种新的耦合电路。该电路采用了一种新的亚阈值区域偏置方法来减小耦合电容的值。在该电路中，耦合电容与普通电容耦合电路相比减少了约98%。此外，所提出的耦合电路具有较高的线性度。采用HSPICE仿真、180nm工艺和1.8V电源对电路进行了性能评估。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Reduction of coupling capacitance, using a capacitor-transistor coupling circuit

In this paper, a new coupling circuit is presented. This circuit uses a new method of subthreshold region biasing to decrease the value of coupling capacitor. In proposed circuit the Coupling capacitor is decreased about 98% in comparison with the ordinary capacitive coupling circuit. In addition, the proposed coupling circuit achieves higher linearity. The performance evaluation of proposed circuit is carried out using HSPICE simulations, 180nm technology and 1.8V power supply.

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2015 9th International Conference on Electrical and Electronics Engineering (ELECO)

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