Accumulator-based compaction for built-in self test of data-path architectures

Accumulators composed of adders and registers are commonly used building blocks in general-purpose computing structures based on data-path architecture. The authors introduce a new accumulator-based compaction scheme for parallel compaction of test responses. The proposed scheme is compatible with the width of the data path, the hardware overhead is minimal, it does not introduce any performance degradation, and the compaction quality is the same as that offered by linear feedback shift registers.<>