{"title":"30nm隧道场效应晶体管与CMOS逆变器特性的比较","authors":"M. Aswathy, N. M. Biju, R. Komaragiri","doi":"10.1109/ICACC.2013.36","DOIUrl":null,"url":null,"abstract":"Tunnel field-effect transistor (TFET) is a promising candidate for the succession of the MOSFET at deca-nanometer dimensions. Tunneling currents are no longer considered as unwanted parasitics in these devices. In this work, the device architecture and performance of both n-type and p-type TFETs with a channel length of 30nm are simulated and studied. Mixed mode simulation of TFET inverter and a comparison with CMOS inverter characteristics show that TFET inverter doesn't need level shifting at the output and can succeed CMOS digital applications.","PeriodicalId":109537,"journal":{"name":"2013 Third International Conference on Advances in Computing and Communications","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Comparison of a 30nm Tunnel Field Effect Transistor and CMOS Inverter Characteristics\",\"authors\":\"M. Aswathy, N. M. Biju, R. Komaragiri\",\"doi\":\"10.1109/ICACC.2013.36\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Tunnel field-effect transistor (TFET) is a promising candidate for the succession of the MOSFET at deca-nanometer dimensions. Tunneling currents are no longer considered as unwanted parasitics in these devices. In this work, the device architecture and performance of both n-type and p-type TFETs with a channel length of 30nm are simulated and studied. Mixed mode simulation of TFET inverter and a comparison with CMOS inverter characteristics show that TFET inverter doesn't need level shifting at the output and can succeed CMOS digital applications.\",\"PeriodicalId\":109537,\"journal\":{\"name\":\"2013 Third International Conference on Advances in Computing and Communications\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-08-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 Third International Conference on Advances in Computing and Communications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICACC.2013.36\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 Third International Conference on Advances in Computing and Communications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICACC.2013.36","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Comparison of a 30nm Tunnel Field Effect Transistor and CMOS Inverter Characteristics
Tunnel field-effect transistor (TFET) is a promising candidate for the succession of the MOSFET at deca-nanometer dimensions. Tunneling currents are no longer considered as unwanted parasitics in these devices. In this work, the device architecture and performance of both n-type and p-type TFETs with a channel length of 30nm are simulated and studied. Mixed mode simulation of TFET inverter and a comparison with CMOS inverter characteristics show that TFET inverter doesn't need level shifting at the output and can succeed CMOS digital applications.