伪cmos电路的噪声裕度分析

2016 7th International Conference on Computer Aided Design for Thin-Film Transistor Technologies (CAD-TFT) Pub Date : 2016-10-01 DOI:10.1109/CAD-TFT.2016.7785043

Q. Zhao, W. Sun, Y. Liu, H. Yang, J. Zhao, X. Guo

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引用次数: 0

摘要

尽管伪CMOS逻辑具有噪声裕度大的优点，但缺乏其分析模型。本文推导了伪cmos(伪D)逻辑电路的静态噪声裕度模型。最后，分析了设计参数对噪声裕度的影响。仿真结果表明，模型误差约为3%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Noise margin analysis for Pseudo-CMOS circuits

Despite the large noise margin merit of pseudo- CMOS logic, its analytical model is absent. In this paper, we derive the static noise margin model for pseudo-CMOS (pseudo- D) logic circuits. Finally, we analyze the impact of design parameters on noise margin. Simulations show the modeling error is about 3%.

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2016 7th International Conference on Computer Aided Design for Thin-Film Transistor Technologies (CAD-TFT)

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