带时钟恢复和集成21dBm功率放大器的5.8GHz低中频多数据速率GFSK收发器

2008 IEEE Radio Frequency Integrated Circuits Symposium Pub Date : 2008-07-15 DOI:10.1109/RFIC.2008.4561433

C. Quek, S. Farahvash, W. Roberts, M. Romney, D. Walker, C. Otten, R. Wei, D. Schwan, M. Mostafa, D. Haab, J. Liu, H. Liem, R. Koupal

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引用次数: 0

摘要

一个高度集成的5.8 GHz收发器，能够支持多种数据速率，在0.18 um SiGe BiCMOS中设计，用于数字无线电话和流媒体音频应用。它还具有时钟数据恢复(CDR)电路，可以与数字接收数据一起提供给基带芯片。在1.536 Mbps和2.048 Mbps下，带集成功率放大器的发射机功耗为185ma，输出功率为20.5 dBm，接收机功耗为65ma，灵敏度分别为-103.5 dBm和-101.5 dBm。活动面积为7.3 mm2。

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A 5.8GHz low-IF multi-data rate GFSK transceiver with clock recovery and integrated 21dBm power amplifier

A highly integrated 5.8 GHz transceiver capable of supporting multiple data rates has been designed in 0.18 um SiGe BiCMOS for digital cordless phones and streaming audio applications. It also has a clock data recovery (CDR) circuit which can be supplied to baseband chips in conjunction with the digital received data. The transmitter with an integrated power amplifier consumes 185 mA achieving an output power of 20.5 dBm and the receiver consumes 65 mA achieving a sensitivity of -103.5 dBm and -101.5 dBm at 1.536 Mbps and 2.048 Mbps respectively. The active area is 7.3 mm2.

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2008 IEEE Radio Frequency Integrated Circuits Symposium

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