Yunfeng Wang, Qing Ye, Jiahan Man, Jim Fan, Tianchun Ye
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引用次数: 0
摘要
本文介绍了一种用于无线接收机的4ghz锁相环的设计。Verilog-A模型用于行为级仿真和布局后仿真。本设计基于中芯国际0.18 um 1P6M CMOS射频工艺。稳定时间为19us，参考杂散为42.2 dB，压控振荡器相位噪声为-115 dBc/Hz@lMHz，锁相环功耗为36 mW。
:This paper presents the design of a 4 GHz PLL used in wireless receiver. The Verilog-A models are used in behavioral level simulation and in post-layout simulation. The design is based on SMIC 0.18 um 1P6M CMOS RF process. The settling time is 19us and the reference spur is 42.2 dB, the phase noise of VCO is -115 dBc/Hz@lMHz, the power dissipation of the PLL is 36 mW.
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