{"title":"递归快速乘法器","authors":"A. Danysh, E. Swartzlander","doi":"10.1109/ACSSC.1998.750853","DOIUrl":null,"url":null,"abstract":"This paper presents a recursive fast multiplication algorithm. The paper defines the algorithm and applies it to two's complement signed multiplication. A step-by-step approach is given that discusses the architectural and logic implementation in detail. A random, self-checking, simulation program verifies the correctness of the recursive multiplication algorithm. The paper analyzes the speed and gate count of the design and compares the results to other multiplier designs.","PeriodicalId":393743,"journal":{"name":"Conference Record of Thirty-Second Asilomar Conference on Signals, Systems and Computers (Cat. No.98CH36284)","volume":"65 6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"34","resultStr":"{\"title\":\"A recursive fast multiplier\",\"authors\":\"A. Danysh, E. Swartzlander\",\"doi\":\"10.1109/ACSSC.1998.750853\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a recursive fast multiplication algorithm. The paper defines the algorithm and applies it to two's complement signed multiplication. A step-by-step approach is given that discusses the architectural and logic implementation in detail. A random, self-checking, simulation program verifies the correctness of the recursive multiplication algorithm. The paper analyzes the speed and gate count of the design and compares the results to other multiplier designs.\",\"PeriodicalId\":393743,\"journal\":{\"name\":\"Conference Record of Thirty-Second Asilomar Conference on Signals, Systems and Computers (Cat. No.98CH36284)\",\"volume\":\"65 6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"34\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Conference Record of Thirty-Second Asilomar Conference on Signals, Systems and Computers (Cat. No.98CH36284)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ACSSC.1998.750853\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Conference Record of Thirty-Second Asilomar Conference on Signals, Systems and Computers (Cat. No.98CH36284)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ACSSC.1998.750853","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper presents a recursive fast multiplication algorithm. The paper defines the algorithm and applies it to two's complement signed multiplication. A step-by-step approach is given that discusses the architectural and logic implementation in detail. A random, self-checking, simulation program verifies the correctness of the recursive multiplication algorithm. The paper analyzes the speed and gate count of the design and compares the results to other multiplier designs.