采用晶体in - ga - zn -oxide晶体管，功率门控的盈亏平衡时间为4.9 μs

2013 IEEE COOL Chips XVI Pub Date : 2013-04-17 DOI:10.1109/CoolChips.2013.6547913

Hidetomo Kobayashi, K. Kato, Takuro Ohmaru, S. Yoneda, T. Nishijima, Shuhei Maeda, K. Ohshima, H. Tamura, Hiroyuki Tomatsu, T. Atsumi, Y. Shionoiri, Y. Maehashi, J. Koyama, S. Yamazaki

{"title":"采用晶体in - ga - zn -oxide晶体管，功率门控的盈亏平衡时间为4.9 μs","authors":"Hidetomo Kobayashi, K. Kato, Takuro Ohmaru, S. Yoneda, T. Nishijima, Shuhei Maeda, K. Ohshima, H. Tamura, Hiroyuki Tomatsu, T. Atsumi, Y. Shionoiri, Y. Maehashi, J. Koyama, S. Yamazaki","doi":"10.1109/CoolChips.2013.6547913","DOIUrl":null,"url":null,"abstract":"A processor having a power management unit (PMU) and an 8-bit CPU including flip-flops with shadow memories is fabricated by 0.5-μm Si and 0.8-μm c-axis-aligned crystalline In-Ga-Zn-oxide (CAAC-IGZO) technology. The shadow memories hold data without power supply utilizing low off-state current of CAAC-IGZO FETs. A break-even time (BET) of 4.9μs has been obtained. Good scalability of the processor in writing data to shadow memories and in area (5.7% overhead or less) is also confirmed through simulation and layout, based on flip-flops using 30-nm Si FETs combined with 0.3-μm CAAC-IGZO FETs which show good electronic characteristics and no overhead in area.","PeriodicalId":340576,"journal":{"name":"2013 IEEE COOL Chips XVI","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"Processor with 4.9-μs break-even time in power gating using crystalline In-Ga-Zn-oxide transistor\",\"authors\":\"Hidetomo Kobayashi, K. Kato, Takuro Ohmaru, S. Yoneda, T. Nishijima, Shuhei Maeda, K. Ohshima, H. Tamura, Hiroyuki Tomatsu, T. Atsumi, Y. Shionoiri, Y. Maehashi, J. Koyama, S. Yamazaki\",\"doi\":\"10.1109/CoolChips.2013.6547913\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A processor having a power management unit (PMU) and an 8-bit CPU including flip-flops with shadow memories is fabricated by 0.5-μm Si and 0.8-μm c-axis-aligned crystalline In-Ga-Zn-oxide (CAAC-IGZO) technology. The shadow memories hold data without power supply utilizing low off-state current of CAAC-IGZO FETs. A break-even time (BET) of 4.9μs has been obtained. Good scalability of the processor in writing data to shadow memories and in area (5.7% overhead or less) is also confirmed through simulation and layout, based on flip-flops using 30-nm Si FETs combined with 0.3-μm CAAC-IGZO FETs which show good electronic characteristics and no overhead in area.\",\"PeriodicalId\":340576,\"journal\":{\"name\":\"2013 IEEE COOL Chips XVI\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-04-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE COOL Chips XVI\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CoolChips.2013.6547913\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE COOL Chips XVI","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CoolChips.2013.6547913","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 16

摘要

采用0.5 μm Si和0.8 μm c轴向晶体In-Ga-Zn-oxide (CAAC-IGZO)技术制备了具有电源管理单元(PMU)和8位CPU(包括带阴影存储器的触发器)的处理器。阴影存储器利用CAAC-IGZO fet的低断开状态电流在没有电源的情况下保存数据。获得了4.9μs的保本时间(BET)。基于30 nm Si fet和0.3 μm CAAC-IGZO fet的触发器的仿真和布局也证实了该处理器在向影子存储器写入数据方面具有良好的可扩展性(开销不超过5.7%)，具有良好的电子特性和面积开销。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Processor with 4.9-μs break-even time in power gating using crystalline In-Ga-Zn-oxide transistor

A processor having a power management unit (PMU) and an 8-bit CPU including flip-flops with shadow memories is fabricated by 0.5-μm Si and 0.8-μm c-axis-aligned crystalline In-Ga-Zn-oxide (CAAC-IGZO) technology. The shadow memories hold data without power supply utilizing low off-state current of CAAC-IGZO FETs. A break-even time (BET) of 4.9μs has been obtained. Good scalability of the processor in writing data to shadow memories and in area (5.7% overhead or less) is also confirmed through simulation and layout, based on flip-flops using 30-nm Si FETs combined with 0.3-μm CAAC-IGZO FETs which show good electronic characteristics and no overhead in area.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2013 IEEE COOL Chips XVI

自引率

0.00%

发文量