Designing a QoS-enabled 2 GHz On-Chip Network Router in 16nm CMOS

With CMOS technology still advancing and 10- to 16-core general-purpose CPUs becoming common, their designing comes with tradeoffs caused by scarce memory bandwidth, limited silicon budget and prevailing wire delays. In this work, we describe the designing of a QoS-enabled 2×7 mesh network router within a budget of a 3VC multiported router in 16nm technology. The design was optimized to reduce cell area, then QoS was enabled by splitting the VCs, and timing constraints were met by splitting the pipeline into three cycles. In our experiments, the proposed scheme demonstrates up to a three-time increase in minimal throughput in uniform traffic at the cost of one percent L3 cache throughput reduction and power increase for all 14 routers with 6 subnets from 2.4 to 2.8 W.