气簇离子束处理提高7nm节点FinFET: MJ: MOL和结界面的自对准接触良率

S. Fan, S. Teehan, K. Chung, Alex Varghese, Mark Lenhardt, P. Montanini, S. Skordas, B. Haran, S. Tsai, R. Xie
{"title":"气簇离子束处理提高7nm节点FinFET: MJ: MOL和结界面的自对准接触良率","authors":"S. Fan, S. Teehan, K. Chung, Alex Varghese, Mark Lenhardt, P. Montanini, S. Skordas, B. Haran, S. Tsai, R. Xie","doi":"10.1109/ASMC.2018.8373209","DOIUrl":null,"url":null,"abstract":"Self-aligned contact (SAC) is required for 7 nm node to reduce susceptibility of contact-to-gate short failures. This requires forming a SAC cap on metal-recessed gate. The SAC cap formation is usually achieved by removing nitride on the field by planarization techniques such CMP (chemical mechanical polishing) or GCIB (gas cluster ion beam) processes. Significant gate stack height variation can be observed lot-to-lot and wafer-to-wafer due to accumulated variations from multiple steps, including several CMP steps, before the SAC cap module, especially during early research and development prior to full optimization of the steps before the SAC cap module. GCIB potentially offers a method by which the early development stage variation due to CMP steps can be reduced, allowing integration and device learning during the early stages of a program. This study shows a comparison of SAC cap formation by CMP only vs. GCIB with integrated metrology enabled location specific processing. By using GCIB with feed-forward scatterometry measurements taken from a 2D measurement pad we have been able to significantly improve both lot-to-lot and wafer-to-wafer variation on early development wafers. This has led to improvement in within wafer SAC cap thickness non-uniformity, wafer to wafer and lot to lot device yield for gate-contact over a CMP-only process flow.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Gas cluster ion beam processing for improved self aligned contact yield at 7 nm node FinFET: MJ: MOL and junction interfaces\",\"authors\":\"S. Fan, S. Teehan, K. Chung, Alex Varghese, Mark Lenhardt, P. Montanini, S. Skordas, B. Haran, S. Tsai, R. Xie\",\"doi\":\"10.1109/ASMC.2018.8373209\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Self-aligned contact (SAC) is required for 7 nm node to reduce susceptibility of contact-to-gate short failures. This requires forming a SAC cap on metal-recessed gate. The SAC cap formation is usually achieved by removing nitride on the field by planarization techniques such CMP (chemical mechanical polishing) or GCIB (gas cluster ion beam) processes. Significant gate stack height variation can be observed lot-to-lot and wafer-to-wafer due to accumulated variations from multiple steps, including several CMP steps, before the SAC cap module, especially during early research and development prior to full optimization of the steps before the SAC cap module. GCIB potentially offers a method by which the early development stage variation due to CMP steps can be reduced, allowing integration and device learning during the early stages of a program. This study shows a comparison of SAC cap formation by CMP only vs. GCIB with integrated metrology enabled location specific processing. By using GCIB with feed-forward scatterometry measurements taken from a 2D measurement pad we have been able to significantly improve both lot-to-lot and wafer-to-wafer variation on early development wafers. This has led to improvement in within wafer SAC cap thickness non-uniformity, wafer to wafer and lot to lot device yield for gate-contact over a CMP-only process flow.\",\"PeriodicalId\":349004,\"journal\":{\"name\":\"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASMC.2018.8373209\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASMC.2018.8373209","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

摘要

7nm节点需要自对准触点(SAC)来降低触点到栅极短失效的敏感性。这需要在金属凹槽门上形成SAC盖。SAC帽的形成通常是通过化学机械抛光(CMP)或气团离子束(GCIB)等平面化技术去除现场的氮化物来实现的。由于在SAC封盖模块之前的多个步骤(包括几个CMP步骤)累积的变化,特别是在SAC封盖模块之前的步骤完全优化之前的早期研究和开发期间,可以观察到批次之间和晶圆之间的栅极堆叠高度的显著变化。GCIB可能提供一种方法,通过这种方法可以减少由于CMP步骤导致的早期开发阶段的变化,从而允许在程序的早期阶段进行集成和设备学习。本研究显示了仅CMP与集成计量支持位置特定处理的GCIB的SAC帽形成的比较。通过使用GCIB和前馈散射测量测量,我们已经能够显著改善早期开发晶圆的批次间和晶圆间的差异。这导致了晶圆内SAC帽厚度不均匀性的改善,晶圆与晶圆之间和批对批设备在仅cmp工艺流程上的栅极接触良率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Gas cluster ion beam processing for improved self aligned contact yield at 7 nm node FinFET: MJ: MOL and junction interfaces
Self-aligned contact (SAC) is required for 7 nm node to reduce susceptibility of contact-to-gate short failures. This requires forming a SAC cap on metal-recessed gate. The SAC cap formation is usually achieved by removing nitride on the field by planarization techniques such CMP (chemical mechanical polishing) or GCIB (gas cluster ion beam) processes. Significant gate stack height variation can be observed lot-to-lot and wafer-to-wafer due to accumulated variations from multiple steps, including several CMP steps, before the SAC cap module, especially during early research and development prior to full optimization of the steps before the SAC cap module. GCIB potentially offers a method by which the early development stage variation due to CMP steps can be reduced, allowing integration and device learning during the early stages of a program. This study shows a comparison of SAC cap formation by CMP only vs. GCIB with integrated metrology enabled location specific processing. By using GCIB with feed-forward scatterometry measurements taken from a 2D measurement pad we have been able to significantly improve both lot-to-lot and wafer-to-wafer variation on early development wafers. This has led to improvement in within wafer SAC cap thickness non-uniformity, wafer to wafer and lot to lot device yield for gate-contact over a CMP-only process flow.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信