Impact of board variables on the thermal performance of a QFN package

The Quad Flat No-Lead (QFN) package, with its exposed die pad soldered to the printed wiring board (PWB), has a thermal performance highly dependent on the PWB design and thermal environment. This paper documents the impact of the following changes to the PWB on the thermal performance of a 44-lead 9/spl times/9 mm QFN package: PWB overall thickness, board area, PWB internal plane thicknesses, number of plated through hole (PTH) vias, PTH via drill diameter, PTH via plating thickness, and PTH via fill material conductivity. The impact of die size and die attach conductivity is also presented in this paper. The effects of these changes are evaluated with a validated finite element model. Two thermal environments are used to evaluate these variables: (1) natural convection with radiation and (2) constant temperature on the bottom side of PWB. Results are listed using two thermal resistances: junction-to-ambient thermal resistance in natural convection on a 2s2p test board (Theta-JMA) according to EIA/JESD51-6 and junction-to-heat sink (Theta-JS) determined with the bottom of the board held at a constant temperature. Theta-JMA is most sensitive to test board area, number of PTH vias, and test board internal plane thickness. Theta-JS is most sensitive to number of PTH vias. The thermal performance of the QFN is also evaluated in two distinct arrangements meant to illustrate the application environment conditions: (1) in a 3/spl times/3 cluster on a board, and (2) on the board where it is attached to an aluminum heat rail. Heat sinking the bottom of the board allows packages to dissipate more heat for a given junction-to-ambient temperature difference than the packages that rely only on natural convection.