{"title":"一种新颖的基于4T异或的1位全加法器设计","authors":"N. Singh, P. Sharma","doi":"10.1109/I2CT.2014.7092062","DOIUrl":null,"url":null,"abstract":"This paper puts forward a methodology for designing 1 bit full adder using a newly proposed 4T xor gate. The 4T xor gate is formed of 2 pMOS and 2 nMOS transistors. The sum is formed using 2 xor gate and the carry is formed using a 2T mux. The resulting 1 bit full adder is made up of 10 transistors. The simulation is done using Cadence Virtuoso Simulator using 180nm technology and 1.8V power supply. The results show the efficiency of the design.","PeriodicalId":384966,"journal":{"name":"International Conference for Convergence for Technology-2014","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A novel 4T XOR based 1 bit full adder design\",\"authors\":\"N. Singh, P. Sharma\",\"doi\":\"10.1109/I2CT.2014.7092062\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper puts forward a methodology for designing 1 bit full adder using a newly proposed 4T xor gate. The 4T xor gate is formed of 2 pMOS and 2 nMOS transistors. The sum is formed using 2 xor gate and the carry is formed using a 2T mux. The resulting 1 bit full adder is made up of 10 transistors. The simulation is done using Cadence Virtuoso Simulator using 180nm technology and 1.8V power supply. The results show the efficiency of the design.\",\"PeriodicalId\":384966,\"journal\":{\"name\":\"International Conference for Convergence for Technology-2014\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-04-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Conference for Convergence for Technology-2014\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/I2CT.2014.7092062\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Conference for Convergence for Technology-2014","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/I2CT.2014.7092062","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper puts forward a methodology for designing 1 bit full adder using a newly proposed 4T xor gate. The 4T xor gate is formed of 2 pMOS and 2 nMOS transistors. The sum is formed using 2 xor gate and the carry is formed using a 2T mux. The resulting 1 bit full adder is made up of 10 transistors. The simulation is done using Cadence Virtuoso Simulator using 180nm technology and 1.8V power supply. The results show the efficiency of the design.
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