H.263视频编码的灵活架构

Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools Pub Date : 2002-09-04 DOI:10.1109/DSD.2002.1115353

M. Garrido, C. Sanz, Marcos Jiménez, J. Meneses

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引用次数: 6

摘要

本文根据Rec. H.263标准，提出了一种灵活高效的视频编码器核心架构。它由一个RISC处理器组成，该处理器控制一组专用处理器的调度，用于变换(DCT和IDCT)，量化(DQ和IQ)，运动估计和运动补偿(ME/MC)。该体系结构还包括用于从摄像机输入视频信号的预处理模块和用于外部视频存储器和H.263比特流生成的接口。该架构已在可合成的Verilog中编写，并使用标准视频序列进行了测试。它还被原型化为基于FPGA和RISC的开发系统。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A flexible architecture for H.263 video coding

In this paper a very flexible and efficient architecture that implements the core of a video coder according to Rec. H.263 is presented. It consists of a RISC processor that controls the scheduling of a set of specialized processors for the transforms (DCT and IDCT), quantizers (DQ and IQ), motion estimation and motion compensation (ME/MC). The architecture also includes preprocessing modules for the input video signal from the camera and interfaces for the external video memory and the H.263 bit-stream generation. The architecture has been written in synthesizable Verilog and tested using standard video sequences. It has also been prototyped into a development system based on an FPGA and a RISC.

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Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools

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