{"title":"采用0.18µm CMOS技术的片上差分电感的2.4GHz共门LNA","authors":"Changgui Lin, T. Kalkur, M. Morin","doi":"10.1109/CONIELECOMP.2009.35","DOIUrl":null,"url":null,"abstract":"A 2.4GHz CMOS differential common-gate low noise amplifier (CGLNA) is presented. It utilizes two on-chip differential inductors instead of four on-chip single-ended inductors in traditional designs, resulting in significantly reduced die area. Furthermore, two noise reduction techniques, i.e. capacitive cross-coupling and MOSFET channel length optimization, are discussed. A prototype was fabricated in a 0.18μm RF CMOS process, and was packaged for testing. The measurement results are in agreement with circuit simulations.","PeriodicalId":292855,"journal":{"name":"2009 International Conference on Electrical, Communications, and Computers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-02-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":"{\"title\":\"A 2.4GHz Common-Gate LNA Using On-Chip Differential Inductors in a 0.18µm CMOS Technology\",\"authors\":\"Changgui Lin, T. Kalkur, M. Morin\",\"doi\":\"10.1109/CONIELECOMP.2009.35\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 2.4GHz CMOS differential common-gate low noise amplifier (CGLNA) is presented. It utilizes two on-chip differential inductors instead of four on-chip single-ended inductors in traditional designs, resulting in significantly reduced die area. Furthermore, two noise reduction techniques, i.e. capacitive cross-coupling and MOSFET channel length optimization, are discussed. A prototype was fabricated in a 0.18μm RF CMOS process, and was packaged for testing. The measurement results are in agreement with circuit simulations.\",\"PeriodicalId\":292855,\"journal\":{\"name\":\"2009 International Conference on Electrical, Communications, and Computers\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-02-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"13\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 International Conference on Electrical, Communications, and Computers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CONIELECOMP.2009.35\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Conference on Electrical, Communications, and Computers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CONIELECOMP.2009.35","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 2.4GHz Common-Gate LNA Using On-Chip Differential Inductors in a 0.18µm CMOS Technology
A 2.4GHz CMOS differential common-gate low noise amplifier (CGLNA) is presented. It utilizes two on-chip differential inductors instead of four on-chip single-ended inductors in traditional designs, resulting in significantly reduced die area. Furthermore, two noise reduction techniques, i.e. capacitive cross-coupling and MOSFET channel length optimization, are discussed. A prototype was fabricated in a 0.18μm RF CMOS process, and was packaged for testing. The measurement results are in agreement with circuit simulations.