{"title":"印刷电子门阵列电路的技术独立产率感知位置和路径策略","authors":"M. Llamas, J. Carrabina, L. Terés","doi":"10.1109/CAD-TFT.2016.7785047","DOIUrl":null,"url":null,"abstract":"We present a new Placement and Routing (P&R) strategy for implementing digital Organic/Flexible/Printed Electronics (PE) circuits based on an Inkjet-configurable Gate Array (IGA) design style together with digital printing personalization.","PeriodicalId":303429,"journal":{"name":"2016 7th International Conference on Computer Aided Design for Thin-Film Transistor Technologies (CAD-TFT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Technology independent yield-aware place & route strategy for printed electronics gate array circuits\",\"authors\":\"M. Llamas, J. Carrabina, L. Terés\",\"doi\":\"10.1109/CAD-TFT.2016.7785047\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a new Placement and Routing (P&R) strategy for implementing digital Organic/Flexible/Printed Electronics (PE) circuits based on an Inkjet-configurable Gate Array (IGA) design style together with digital printing personalization.\",\"PeriodicalId\":303429,\"journal\":{\"name\":\"2016 7th International Conference on Computer Aided Design for Thin-Film Transistor Technologies (CAD-TFT)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 7th International Conference on Computer Aided Design for Thin-Film Transistor Technologies (CAD-TFT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CAD-TFT.2016.7785047\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 7th International Conference on Computer Aided Design for Thin-Film Transistor Technologies (CAD-TFT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CAD-TFT.2016.7785047","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Technology independent yield-aware place & route strategy for printed electronics gate array circuits
We present a new Placement and Routing (P&R) strategy for implementing digital Organic/Flexible/Printed Electronics (PE) circuits based on an Inkjet-configurable Gate Array (IGA) design style together with digital printing personalization.