C. D'Alessandro, N. Minas, K. Heron, D. Kinniment, A. Yakovlev
{"title":"基于时间-数字转换的NoC通信策略","authors":"C. D'Alessandro, N. Minas, K. Heron, D. Kinniment, A. Yakovlev","doi":"10.1109/NOCS.2007.29","DOIUrl":null,"url":null,"abstract":"A radical approach to high-speed on-chip communication between computational modules is proposed. Data communication is performed over multiple serial buses, where the time difference between events is used to encode and decode data on a number of wires. We present results obtained through a proof-of-concept implementation on FPGA and simulations on a 0.18mum technology","PeriodicalId":132772,"journal":{"name":"First International Symposium on Networks-on-Chip (NOCS'07)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"NoC Communication Strategies Using Time-to-Digital Conversion\",\"authors\":\"C. D'Alessandro, N. Minas, K. Heron, D. Kinniment, A. Yakovlev\",\"doi\":\"10.1109/NOCS.2007.29\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A radical approach to high-speed on-chip communication between computational modules is proposed. Data communication is performed over multiple serial buses, where the time difference between events is used to encode and decode data on a number of wires. We present results obtained through a proof-of-concept implementation on FPGA and simulations on a 0.18mum technology\",\"PeriodicalId\":132772,\"journal\":{\"name\":\"First International Symposium on Networks-on-Chip (NOCS'07)\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-05-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"First International Symposium on Networks-on-Chip (NOCS'07)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NOCS.2007.29\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"First International Symposium on Networks-on-Chip (NOCS'07)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NOCS.2007.29","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
NoC Communication Strategies Using Time-to-Digital Conversion
A radical approach to high-speed on-chip communication between computational modules is proposed. Data communication is performed over multiple serial buses, where the time difference between events is used to encode and decode data on a number of wires. We present results obtained through a proof-of-concept implementation on FPGA and simulations on a 0.18mum technology