Nikolaos Eftaxiopoulos-Sarris, N. Axelos, K. Pekmestzi
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In this paper we propose a leakage-aware soft error tolerant storage element, implementable in standard CMOS technology and able to operate both as a CAM and as a TCAM cell. The proposed cell is immune to SNUs (Single Node Upsets) when operating as a CAM cell and demonstrates partial resilience (75%) when operating as a TCAM cell. Simulation results in SPICE at a 45nm PTM technology show a significant reduction in leakage dissipation compared to the standard but unprotected 6T-based TCAM cell as well as compared to conventional DICE-based CAM/TCAM solutions.
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