无结晶体管栅内特性与沟道长度和掺杂浓度的关系

2013 IEEE International Conference of Electron Devices and Solid-state Circuits Pub Date : 2013-06-03 DOI:10.1109/EDSSC.2013.6628156

Pankaj Kumar, Chitrakant Sahu, Anup Shrivastava, P. Kondekar, Jawar Singh

{"title":"无结晶体管栅内特性与沟道长度和掺杂浓度的关系","authors":"Pankaj Kumar, Chitrakant Sahu, Anup Shrivastava, P. Kondekar, Jawar Singh","doi":"10.1109/EDSSC.2013.6628156","DOIUrl":null,"url":null,"abstract":"A novel device structure has been proposed in this paper for junctionless transistor with gate inside device architecture. Its characteristics are demonstrated at gate length of 30 nm. The proposed device shows very good ION/IOFF ratio approximately 108, excellent sub-threshold swing (SS) 63 mV=dec, improved drain induced barrier lowering (DIBL) 40 mV with high ON-state current and extremely low leakage current. The various device parameters are also observed for channel length of 22 nm and 14 nm. The device shows improved short-channel effects with no junction between channel and source/drain, which greatly simplifies the fabrication process at nano scale level. A 3-D ATLAS numerical simulation has been carried out for the proposed device structure.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"98 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Characteristics of gate inside junctionless transistor with channel length and doping concentration\",\"authors\":\"Pankaj Kumar, Chitrakant Sahu, Anup Shrivastava, P. Kondekar, Jawar Singh\",\"doi\":\"10.1109/EDSSC.2013.6628156\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel device structure has been proposed in this paper for junctionless transistor with gate inside device architecture. Its characteristics are demonstrated at gate length of 30 nm. The proposed device shows very good ION/IOFF ratio approximately 108, excellent sub-threshold swing (SS) 63 mV=dec, improved drain induced barrier lowering (DIBL) 40 mV with high ON-state current and extremely low leakage current. The various device parameters are also observed for channel length of 22 nm and 14 nm. The device shows improved short-channel effects with no junction between channel and source/drain, which greatly simplifies the fabrication process at nano scale level. A 3-D ATLAS numerical simulation has been carried out for the proposed device structure.\",\"PeriodicalId\":333267,\"journal\":{\"name\":\"2013 IEEE International Conference of Electron Devices and Solid-state Circuits\",\"volume\":\"98 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-06-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE International Conference of Electron Devices and Solid-state Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDSSC.2013.6628156\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2013.6628156","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

本文提出了一种新的器件结构，用于器件结构内部为栅极的无结晶体管。在栅极长度为30 nm处证明了其特性。该器件具有良好的ION/IOFF比，约为108，优良的亚阈值摆幅(SS)为63 mV=dec，改进的漏极抑制(DIBL)为40 mV，具有高导通电流和极低的漏电流。在通道长度为22 nm和14 nm时，还观察了不同的器件参数。该器件具有改进的短沟道效应，沟道与源/漏极之间无结，大大简化了纳米级的制造工艺。对所提出的器件结构进行了三维ATLAS数值模拟。

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Characteristics of gate inside junctionless transistor with channel length and doping concentration

A novel device structure has been proposed in this paper for junctionless transistor with gate inside device architecture. Its characteristics are demonstrated at gate length of 30 nm. The proposed device shows very good ION/IOFF ratio approximately 108, excellent sub-threshold swing (SS) 63 mV=dec, improved drain induced barrier lowering (DIBL) 40 mV with high ON-state current and extremely low leakage current. The various device parameters are also observed for channel length of 22 nm and 14 nm. The device shows improved short-channel effects with no junction between channel and source/drain, which greatly simplifies the fabrication process at nano scale level. A 3-D ATLAS numerical simulation has been carried out for the proposed device structure.

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来源期刊

2013 IEEE International Conference of Electron Devices and Solid-state Circuits

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