具有单事件效应补偿的65nm CMOS平移暂存缓冲器逻辑元件设计

V. Stenin, A. V. Antonyuk, P. Stepanov, Yu. V. Katunin
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引用次数: 12

摘要

设计了具有单事件补偿的平移缓冲逻辑元件,并在65纳米CMOS设计规则上进行了仿真。通过强化设计,使单核粒子冲击下的扰动和单事件瞬态对MOS逻辑元件的影响最小化。容错设计的基础是在内容可寻址存储器(CAM)单元和RAM单元的数组中强化公共矩阵的主行元素。CAM的符合逻辑的基础是组合逻辑元件,并采用屏蔽和补偿的单事件补偿。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design of logical elements for the 65-nm CMOS translation lookaside buffer with compensation of single events effects
Logical elements for translation lookaside buffers were designed with single-event compensations and simulated on the bulk 65-nm CMOS design rule. The effects of upsets and single-event transients under impacts of single nuclear particles on MOS logical elements were minimized by the hardening the design. The basis of the fault-tolerant design is the hardened main row elements of the common matrix in arrays of Content-Addressable Memory (CAM) cells and RAM cells. The basis of the coincidence logic of CAM is combinational logic elements with the single-event compensation using masking and compensation.
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