V. Stenin, A. V. Antonyuk, P. Stepanov, Yu. V. Katunin
{"title":"具有单事件效应补偿的65nm CMOS平移暂存缓冲器逻辑元件设计","authors":"V. Stenin, A. V. Antonyuk, P. Stepanov, Yu. V. Katunin","doi":"10.1109/SIBCON.2017.7998513","DOIUrl":null,"url":null,"abstract":"Logical elements for translation lookaside buffers were designed with single-event compensations and simulated on the bulk 65-nm CMOS design rule. The effects of upsets and single-event transients under impacts of single nuclear particles on MOS logical elements were minimized by the hardening the design. The basis of the fault-tolerant design is the hardened main row elements of the common matrix in arrays of Content-Addressable Memory (CAM) cells and RAM cells. The basis of the coincidence logic of CAM is combinational logic elements with the single-event compensation using masking and compensation.","PeriodicalId":190182,"journal":{"name":"2017 International Siberian Conference on Control and Communications (SIBCON)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-06-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"Design of logical elements for the 65-nm CMOS translation lookaside buffer with compensation of single events effects\",\"authors\":\"V. Stenin, A. V. Antonyuk, P. Stepanov, Yu. V. Katunin\",\"doi\":\"10.1109/SIBCON.2017.7998513\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Logical elements for translation lookaside buffers were designed with single-event compensations and simulated on the bulk 65-nm CMOS design rule. The effects of upsets and single-event transients under impacts of single nuclear particles on MOS logical elements were minimized by the hardening the design. The basis of the fault-tolerant design is the hardened main row elements of the common matrix in arrays of Content-Addressable Memory (CAM) cells and RAM cells. The basis of the coincidence logic of CAM is combinational logic elements with the single-event compensation using masking and compensation.\",\"PeriodicalId\":190182,\"journal\":{\"name\":\"2017 International Siberian Conference on Control and Communications (SIBCON)\",\"volume\":\"32 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-06-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 International Siberian Conference on Control and Communications (SIBCON)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SIBCON.2017.7998513\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International Siberian Conference on Control and Communications (SIBCON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIBCON.2017.7998513","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of logical elements for the 65-nm CMOS translation lookaside buffer with compensation of single events effects
Logical elements for translation lookaside buffers were designed with single-event compensations and simulated on the bulk 65-nm CMOS design rule. The effects of upsets and single-event transients under impacts of single nuclear particles on MOS logical elements were minimized by the hardening the design. The basis of the fault-tolerant design is the hardened main row elements of the common matrix in arrays of Content-Addressable Memory (CAM) cells and RAM cells. The basis of the coincidence logic of CAM is combinational logic elements with the single-event compensation using masking and compensation.