测试嵌入式存储器的最新技术和未来趋势

Records of the 2004 International Workshop on Memory Technology, Design and Testing, 2004. Pub Date : 2004-08-09 DOI:10.1109/MTDT.2004.23

S. Hamdioui, G. Gaydadjiev, A. V. Goor

{"title":"测试嵌入式存储器的最新技术和未来趋势","authors":"S. Hamdioui, G. Gaydadjiev, A. V. Goor","doi":"10.1109/MTDT.2004.23","DOIUrl":null,"url":null,"abstract":"According to the International Technology Roadmap for Semiconductors (ITRS 2001), embedded memories will continue to dominate the increasing system on chips (SoCs) content in the next years, approaching 94% in about 10 years. Therefore the memory yield will have a dramatical impact on the overall defect-per-million (DPM) level, hence on the overall SoC yield. Meeting a high memory yield requires understanding memory designs, modelling their faulty behaviors in the presence of defects, designing adequate tests and diagnosis strategies as well as efficient repair schemes. This paper presents the state of art in memory testing including fault modeling, test design, built-in-self-test (BIST) and built-in-self-repair (BISR). Further research challenges and opportunities are discussed in enabling testing (embedded) memories, which use deep submicron technologies.","PeriodicalId":415606,"journal":{"name":"Records of the 2004 International Workshop on Memory Technology, Design and Testing, 2004.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"86","resultStr":"{\"title\":\"The state-of-art and future trends in testing embedded memories\",\"authors\":\"S. Hamdioui, G. Gaydadjiev, A. V. Goor\",\"doi\":\"10.1109/MTDT.2004.23\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"According to the International Technology Roadmap for Semiconductors (ITRS 2001), embedded memories will continue to dominate the increasing system on chips (SoCs) content in the next years, approaching 94% in about 10 years. Therefore the memory yield will have a dramatical impact on the overall defect-per-million (DPM) level, hence on the overall SoC yield. Meeting a high memory yield requires understanding memory designs, modelling their faulty behaviors in the presence of defects, designing adequate tests and diagnosis strategies as well as efficient repair schemes. This paper presents the state of art in memory testing including fault modeling, test design, built-in-self-test (BIST) and built-in-self-repair (BISR). Further research challenges and opportunities are discussed in enabling testing (embedded) memories, which use deep submicron technologies.\",\"PeriodicalId\":415606,\"journal\":{\"name\":\"Records of the 2004 International Workshop on Memory Technology, Design and Testing, 2004.\",\"volume\":\"6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-08-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"86\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Records of the 2004 International Workshop on Memory Technology, Design and Testing, 2004.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MTDT.2004.23\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Records of the 2004 International Workshop on Memory Technology, Design and Testing, 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTDT.2004.23","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 86

摘要

根据国际半导体技术路线图(ITRS 2001)，嵌入式存储器将在未来几年继续主导不断增长的片上系统(soc)内容，在大约10年内接近94%。因此，内存产量将对整体百万分缺缺率(DPM)水平产生重大影响，从而对整体SoC产量产生重大影响。实现高内存产量需要理解内存设计，在存在缺陷的情况下对其错误行为进行建模，设计适当的测试和诊断策略以及有效的修复方案。本文介绍了存储器测试技术的发展现状，包括故障建模、测试设计、内置自检和内置自修复。进一步的研究挑战和机遇进行了讨论，使测试(嵌入式)存储器，使用深亚微米技术。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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The state-of-art and future trends in testing embedded memories

According to the International Technology Roadmap for Semiconductors (ITRS 2001), embedded memories will continue to dominate the increasing system on chips (SoCs) content in the next years, approaching 94% in about 10 years. Therefore the memory yield will have a dramatical impact on the overall defect-per-million (DPM) level, hence on the overall SoC yield. Meeting a high memory yield requires understanding memory designs, modelling their faulty behaviors in the presence of defects, designing adequate tests and diagnosis strategies as well as efficient repair schemes. This paper presents the state of art in memory testing including fault modeling, test design, built-in-self-test (BIST) and built-in-self-repair (BISR). Further research challenges and opportunities are discussed in enabling testing (embedded) memories, which use deep submicron technologies.

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Records of the 2004 International Workshop on Memory Technology, Design and Testing, 2004.

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