C. Nanda, J. Mukhopadhyay, Debashis Mandal, S. Chakrabarti
{"title":"用于心电采集系统的高直流电极偏移抵消的1v CMOS仪表放大器","authors":"C. Nanda, J. Mukhopadhyay, Debashis Mandal, S. Chakrabarti","doi":"10.1109/TECHSYM.2010.5469187","DOIUrl":null,"url":null,"abstract":"A new circuit topology for a low voltage, low noise instrumentation amplifier (IA) applicable for electrocardiogram signal acquisition system is designed. This circuit is based on the current feedback topology, which is implemented using folded cascode structure at both input and output stages. This helps to sense very low common mode voltage. Achieved input common mode range (ICMR) is 71.43 – 700 mV. DC electrode offset cancellation circuit is realized to remove DC electrode offset along with the low frequency noise. The IA can withstand a high DC electrode offset of ±18 mV. It also has a wide input dynamic range of ±1 µV to ±1 mV. The voltage gain is around 38 dB. It consumes 110 µW power with a supply voltage of 1 V. A high common mode rejection ratio (CMRR) of 80 dB is achieved. The integrated input referred noise is 1.64 µVrms (0.1 Hz – 150 Hz). This design is implemented in 0.18 µm standard CMOS process.","PeriodicalId":262830,"journal":{"name":"2010 IEEE Students Technology Symposium (TechSym)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":"{\"title\":\"1 V CMOS instrumentation amplifier with high DC electrode offset cancellation for ECG acquisition systems\",\"authors\":\"C. Nanda, J. Mukhopadhyay, Debashis Mandal, S. Chakrabarti\",\"doi\":\"10.1109/TECHSYM.2010.5469187\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new circuit topology for a low voltage, low noise instrumentation amplifier (IA) applicable for electrocardiogram signal acquisition system is designed. This circuit is based on the current feedback topology, which is implemented using folded cascode structure at both input and output stages. This helps to sense very low common mode voltage. Achieved input common mode range (ICMR) is 71.43 – 700 mV. DC electrode offset cancellation circuit is realized to remove DC electrode offset along with the low frequency noise. The IA can withstand a high DC electrode offset of ±18 mV. It also has a wide input dynamic range of ±1 µV to ±1 mV. The voltage gain is around 38 dB. It consumes 110 µW power with a supply voltage of 1 V. A high common mode rejection ratio (CMRR) of 80 dB is achieved. The integrated input referred noise is 1.64 µVrms (0.1 Hz – 150 Hz). This design is implemented in 0.18 µm standard CMOS process.\",\"PeriodicalId\":262830,\"journal\":{\"name\":\"2010 IEEE Students Technology Symposium (TechSym)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-04-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"19\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 IEEE Students Technology Symposium (TechSym)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TECHSYM.2010.5469187\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE Students Technology Symposium (TechSym)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TECHSYM.2010.5469187","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
1 V CMOS instrumentation amplifier with high DC electrode offset cancellation for ECG acquisition systems
A new circuit topology for a low voltage, low noise instrumentation amplifier (IA) applicable for electrocardiogram signal acquisition system is designed. This circuit is based on the current feedback topology, which is implemented using folded cascode structure at both input and output stages. This helps to sense very low common mode voltage. Achieved input common mode range (ICMR) is 71.43 – 700 mV. DC electrode offset cancellation circuit is realized to remove DC electrode offset along with the low frequency noise. The IA can withstand a high DC electrode offset of ±18 mV. It also has a wide input dynamic range of ±1 µV to ±1 mV. The voltage gain is around 38 dB. It consumes 110 µW power with a supply voltage of 1 V. A high common mode rejection ratio (CMRR) of 80 dB is achieved. The integrated input referred noise is 1.64 µVrms (0.1 Hz – 150 Hz). This design is implemented in 0.18 µm standard CMOS process.