{"title":"单芯片公钥加密子系统","authors":"P. Ivey, A. Cox, J. Harbridge, J. Oldfield","doi":"10.1109/4.34094","DOIUrl":null,"url":null,"abstract":"A single chip system (figure 1) capable of encryption using the Rivest, Shamir and Adleman (RSA) algorithm at rates significantly higher than other implementations is reported. The chip uses a self-timed methodology and has been implemented in a 2 micron technology. The chip is a complete system and includes registers for the storage of keys for duplex operation. It is provided with a standard interface to a number of common microprocessors.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"A Single Chip Public Key Encryption Sub-System\",\"authors\":\"P. Ivey, A. Cox, J. Harbridge, J. Oldfield\",\"doi\":\"10.1109/4.34094\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A single chip system (figure 1) capable of encryption using the Rivest, Shamir and Adleman (RSA) algorithm at rates significantly higher than other implementations is reported. The chip uses a self-timed methodology and has been implemented in a 2 micron technology. The chip is a complete system and includes registers for the storage of keys for duplex operation. It is provided with a standard interface to a number of common microprocessors.\",\"PeriodicalId\":197244,\"journal\":{\"name\":\"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/4.34094\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/4.34094","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A single chip system (figure 1) capable of encryption using the Rivest, Shamir and Adleman (RSA) algorithm at rates significantly higher than other implementations is reported. The chip uses a self-timed methodology and has been implemented in a 2 micron technology. The chip is a complete system and includes registers for the storage of keys for duplex operation. It is provided with a standard interface to a number of common microprocessors.