单芯片公钥加密子系统

P. Ivey, A. Cox, J. Harbridge, J. Oldfield
{"title":"单芯片公钥加密子系统","authors":"P. Ivey, A. Cox, J. Harbridge, J. Oldfield","doi":"10.1109/4.34094","DOIUrl":null,"url":null,"abstract":"A single chip system (figure 1) capable of encryption using the Rivest, Shamir and Adleman (RSA) algorithm at rates significantly higher than other implementations is reported. The chip uses a self-timed methodology and has been implemented in a 2 micron technology. The chip is a complete system and includes registers for the storage of keys for duplex operation. It is provided with a standard interface to a number of common microprocessors.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"A Single Chip Public Key Encryption Sub-System\",\"authors\":\"P. Ivey, A. Cox, J. Harbridge, J. Oldfield\",\"doi\":\"10.1109/4.34094\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A single chip system (figure 1) capable of encryption using the Rivest, Shamir and Adleman (RSA) algorithm at rates significantly higher than other implementations is reported. The chip uses a self-timed methodology and has been implemented in a 2 micron technology. The chip is a complete system and includes registers for the storage of keys for duplex operation. It is provided with a standard interface to a number of common microprocessors.\",\"PeriodicalId\":197244,\"journal\":{\"name\":\"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/4.34094\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/4.34094","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11

摘要

据报道,一个单芯片系统(图1)能够使用Rivest, Shamir和Adleman (RSA)算法进行加密,其速率明显高于其他实现。该芯片采用自定时方法,并以2微米技术实现。该芯片是一个完整的系统,包括用于存储双工操作的键的寄存器。它提供了一个标准接口到一些常见的微处理器。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Single Chip Public Key Encryption Sub-System
A single chip system (figure 1) capable of encryption using the Rivest, Shamir and Adleman (RSA) algorithm at rates significantly higher than other implementations is reported. The chip uses a self-timed methodology and has been implemented in a 2 micron technology. The chip is a complete system and includes registers for the storage of keys for duplex operation. It is provided with a standard interface to a number of common microprocessors.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信