{"title":"创新实践11C:韧性","authors":"Chen-Yong Cher, Mohan J. Kumar","doi":"10.1109/VTS.2013.6548943","DOIUrl":null,"url":null,"abstract":"Software Hardware co-design is a key mechanism to realizing reliability at platform level. While error avoidance is the ideal, it is not always practical in an economic sense. Often used technique is to detect errors in hardware and implement the recovery in coordination with software. This talk will discuss some examples of such coordination on Intel Xeon (e.g., DIMM Sparing, MCA recovery) and the implications of this type of solution such as platform validation, interface standardization, software enablement, etc.","PeriodicalId":138435,"journal":{"name":"2013 IEEE 31st VLSI Test Symposium (VTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-04-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Innovative practices session 11C: Resilience\",\"authors\":\"Chen-Yong Cher, Mohan J. Kumar\",\"doi\":\"10.1109/VTS.2013.6548943\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Software Hardware co-design is a key mechanism to realizing reliability at platform level. While error avoidance is the ideal, it is not always practical in an economic sense. Often used technique is to detect errors in hardware and implement the recovery in coordination with software. This talk will discuss some examples of such coordination on Intel Xeon (e.g., DIMM Sparing, MCA recovery) and the implications of this type of solution such as platform validation, interface standardization, software enablement, etc.\",\"PeriodicalId\":138435,\"journal\":{\"name\":\"2013 IEEE 31st VLSI Test Symposium (VTS)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-04-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE 31st VLSI Test Symposium (VTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTS.2013.6548943\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE 31st VLSI Test Symposium (VTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTS.2013.6548943","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Software Hardware co-design is a key mechanism to realizing reliability at platform level. While error avoidance is the ideal, it is not always practical in an economic sense. Often used technique is to detect errors in hardware and implement the recovery in coordination with software. This talk will discuss some examples of such coordination on Intel Xeon (e.g., DIMM Sparing, MCA recovery) and the implications of this type of solution such as platform validation, interface standardization, software enablement, etc.
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