{"title":"在GDT中处理可更新的布局设计","authors":"Huamao Liu","doi":"10.1109/ICSICT.1995.503373","DOIUrl":null,"url":null,"abstract":"In this paper, we introduce a method of generating process independent standard cell library and implementing the chip layout with automation tools in GDT. The VLSI designer is able to emigrate their original product to a new developed fabrication process.","PeriodicalId":286176,"journal":{"name":"Proceedings of 4th International Conference on Solid-State and IC Technology","volume":"92 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Process updatable layout design in GDT\",\"authors\":\"Huamao Liu\",\"doi\":\"10.1109/ICSICT.1995.503373\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we introduce a method of generating process independent standard cell library and implementing the chip layout with automation tools in GDT. The VLSI designer is able to emigrate their original product to a new developed fabrication process.\",\"PeriodicalId\":286176,\"journal\":{\"name\":\"Proceedings of 4th International Conference on Solid-State and IC Technology\",\"volume\":\"92 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-10-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 4th International Conference on Solid-State and IC Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSICT.1995.503373\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 4th International Conference on Solid-State and IC Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT.1995.503373","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper, we introduce a method of generating process independent standard cell library and implementing the chip layout with automation tools in GDT. The VLSI designer is able to emigrate their original product to a new developed fabrication process.