{"title":"频率低于10hz的模拟滤波器的集成限制","authors":"W. Deguelle","doi":"10.1109/ESSCIRC.1988.5468391","DOIUrl":null,"url":null,"abstract":"Possibilities and limitations are considered of realizing integrated analog filters with cut off frequencies below 10 Hz. To arrive at an acceptable low chip-area, electronic multiplication is required to enhance the time-constant(s). It is recognized that for a given supply voltage electronic multiplication reduces the dynamic range because of noise-and DC-offset multiplication. As an example a 10 Hz low-pass filter has been successfully integrated on 0.4 sq. mm of chip area in a BICMOS process.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"24","resultStr":"{\"title\":\"Limitations on the Integration of Analog Filters for Frequencies Below 10 Hz\",\"authors\":\"W. Deguelle\",\"doi\":\"10.1109/ESSCIRC.1988.5468391\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Possibilities and limitations are considered of realizing integrated analog filters with cut off frequencies below 10 Hz. To arrive at an acceptable low chip-area, electronic multiplication is required to enhance the time-constant(s). It is recognized that for a given supply voltage electronic multiplication reduces the dynamic range because of noise-and DC-offset multiplication. As an example a 10 Hz low-pass filter has been successfully integrated on 0.4 sq. mm of chip area in a BICMOS process.\",\"PeriodicalId\":197244,\"journal\":{\"name\":\"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"24\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.1988.5468391\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.1988.5468391","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Limitations on the Integration of Analog Filters for Frequencies Below 10 Hz
Possibilities and limitations are considered of realizing integrated analog filters with cut off frequencies below 10 Hz. To arrive at an acceptable low chip-area, electronic multiplication is required to enhance the time-constant(s). It is recognized that for a given supply voltage electronic multiplication reduces the dynamic range because of noise-and DC-offset multiplication. As an example a 10 Hz low-pass filter has been successfully integrated on 0.4 sq. mm of chip area in a BICMOS process.
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