三维网状网络的近最优遗忘路由

R. Ramanujam, Bill Lin
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引用次数: 28

摘要

三维(3D)硅集成技术的日益可行性为芯片架构创新开辟了新的机会。一个方向是将基于二维网格的平铺式芯片多处理器架构扩展到三维空间。在本文中,我们重点研究了这种三维网格网络的有效路由算法。在二维网格网络的情况下,吞吐量和延迟是路由算法的重要设计指标。现有的路由算法要么存在较差的最坏情况吞吐量(DOR、ROMM),要么存在较差的延迟(VAL)。虽然本文提出的最小路由算法O1TURN在二维情况下已经达到了接近最优的最坏情况吞吐量,但最优性结果并没有扩展到更高的维度。对于3D和高维网格,O1TURN的最坏吞吐量会大大降低。本文的主要贡献是为三维网格网络设计了一种新的无关路由算法,称为随机部分最小(RPM)路由。可以证明,当网络基数k为偶数时,RPM可以实现3D网格的最优最坏情况吞吐量,并且在k为奇数时最优最坏情况吞吐量的1/k2范围内。当在8 × 8 × 8拓扑上平均超过100万个随机流量模式时,RPM的平均吞吐量比VAL、DOR、rom和O1TURN分别高出33.3%、111%、47%和30%。最后,VAL在DOR的平均延迟中以2的惩罚因子实现最优最坏情况吞吐量,而RPM以更小的1.33因子实现(接近)最优最坏情况吞吐量。在实践中,RPM的平均延迟预计更接近最小路由,因为3D网格网络在3D芯片设计中不期望是对称的。可用设备层的数量预计要比可以沿设备层边缘放置的处理器块的数量少得多。对于实际的非对称3D网格配置,RPM的平均延迟降低到DOR的1.11倍。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Near-optimal oblivious routing on three-dimensional mesh networks
The increasing viability of three dimensional (3D) silicon integration technology has opened new opportunities for chip architecture innovations. One direction is in the extension of two-dimensional (2D) mesh-based tiled chip-multiprocessor architectures into three dimensions. In this paper, we focus on efficient routing algorithms for such 3D mesh networks. As in the case of 2D mesh networks, throughput and latency are important design metrics for routing algorithms. Existing routing algorithms suffer from either poor worst-case throughput (DOR , ROMM) or poor latency (VAL). Although the minimal routing algorithm O1TURN proposed in already achieves near-optimal worst-case throughput for the 2D case, the optimality result does not extend to higher dimensions. For 3D and higher dimensional meshes, the worst-case throughput of O1TURN degrades tremendously. The main contribution of this paper is the design of a new oblivious routing algorithm for 3D mesh networks called randomized partially-minimal (RPM) routing. RPM provably achieves optimal worst-case throughput for 3D meshes when the network radix k is even and within a factor of 1/k2 of optimal worst-case throughput when k is odd. RPM also outperforms VAL, DOR, ROMM, and O1TURN in average-case throughput by 33.3%, 111%, 47%, and 30%, respectively when averaged over one million random traffic patterns on an 8 times 8 times 8 topology. Finally, whereas VAL achieves optimal worst-case throughput at a penalty factor of 2 in average latency over DOR, RPM achieves (near) optimal worst-case throughput with a much smaller factor of 1.33. In practice, the average latency of RPM is expected to be closer to minimal routing because 3D mesh networks are not expected to be symmetric in 3D chip designs. The number of available device layers is expected to be much less than the number of processor tiles that can be placed along an edge of a device layer. For practical asymmetric 3D mesh configurations, the average latency of RPM reduces to just a factor of 1.11 of DOR.
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