采用选择性CVD-W制备低阻t型栅极的高性能0.1-/spl μ m以下CMOS

1995 Symposium on VLSI Technology. Digest of Technical Papers Pub Date : 1995-06-06 DOI:10.1109/VLSIT.1995.520884

D. Hisamoto, K. Umeda, Y. Nakamura, N. Kobayashi, S. Kimura, R. Nagai

{"title":"采用选择性CVD-W制备低阻t型栅极的高性能0.1-/spl μ m以下CMOS","authors":"D. Hisamoto, K. Umeda, Y. Nakamura, N. Kobayashi, S. Kimura, R. Nagai","doi":"10.1109/VLSIT.1995.520884","DOIUrl":null,"url":null,"abstract":"This paper describes the high performance of sub-0.1-/spl mu/m T-shaped gate CMOS devices fabricated by using selective W growth. The W growth achieves low-resistance gates smaller than 0.1 /spl mu/m; counter doping achieves threshold voltage scaling, resulting in a ring-oscillator gate-delay time of 21 psec.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"High-performance sub-0.1-/spl mu/m CMOS with low-resistance T-shaped gates fabricated by selective CVD-W\",\"authors\":\"D. Hisamoto, K. Umeda, Y. Nakamura, N. Kobayashi, S. Kimura, R. Nagai\",\"doi\":\"10.1109/VLSIT.1995.520884\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the high performance of sub-0.1-/spl mu/m T-shaped gate CMOS devices fabricated by using selective W growth. The W growth achieves low-resistance gates smaller than 0.1 /spl mu/m; counter doping achieves threshold voltage scaling, resulting in a ring-oscillator gate-delay time of 21 psec.\",\"PeriodicalId\":328379,\"journal\":{\"name\":\"1995 Symposium on VLSI Technology. Digest of Technical Papers\",\"volume\":\"31 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-06-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1995 Symposium on VLSI Technology. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.1995.520884\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1995 Symposium on VLSI Technology. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1995.520884","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

摘要

本文介绍了采用选择性W生长方法制备的性能低于0.1-/spl μ m的t型栅极CMOS器件。W生长实现了小于0.1 /spl mu/m的低阻栅;反掺杂实现阈值电压缩放，导致环振荡器门延迟时间为21 psec。

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High-performance sub-0.1-/spl mu/m CMOS with low-resistance T-shaped gates fabricated by selective CVD-W

This paper describes the high performance of sub-0.1-/spl mu/m T-shaped gate CMOS devices fabricated by using selective W growth. The W growth achieves low-resistance gates smaller than 0.1 /spl mu/m; counter doping achieves threshold voltage scaling, resulting in a ring-oscillator gate-delay time of 21 psec.

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1995 Symposium on VLSI Technology. Digest of Technical Papers

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