{"title":"一种新型级联放大器带宽增强技术","authors":"S. Somvanshi, J. Yousuf","doi":"10.1109/ISCIT.2008.4700229","DOIUrl":null,"url":null,"abstract":"In this paper, a new technique is presented to increase the bandwidth for a single stage amplifier. Usually, -3 dB bandwidth of single stage amplifier is in few MHz. High output impedance and subsequent capacitive loading decrease the bandwidth of amplifier. The presented technique uses a load which itself acts as bandwidth enhancer. This high speed amplifier is designed on 180 nm CMOS technology, operates at 2.5 V power supply. This amplifier is succeeded by an output buffer to achieve a better linearity, high output swing and required output impedance for matching.","PeriodicalId":215340,"journal":{"name":"2008 International Symposium on Communications and Information Technologies","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A Novel Bandwidth Enhancement Technique for Cascode Amplifier\",\"authors\":\"S. Somvanshi, J. Yousuf\",\"doi\":\"10.1109/ISCIT.2008.4700229\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a new technique is presented to increase the bandwidth for a single stage amplifier. Usually, -3 dB bandwidth of single stage amplifier is in few MHz. High output impedance and subsequent capacitive loading decrease the bandwidth of amplifier. The presented technique uses a load which itself acts as bandwidth enhancer. This high speed amplifier is designed on 180 nm CMOS technology, operates at 2.5 V power supply. This amplifier is succeeded by an output buffer to achieve a better linearity, high output swing and required output impedance for matching.\",\"PeriodicalId\":215340,\"journal\":{\"name\":\"2008 International Symposium on Communications and Information Technologies\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-12-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 International Symposium on Communications and Information Technologies\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCIT.2008.4700229\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 International Symposium on Communications and Information Technologies","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCIT.2008.4700229","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Novel Bandwidth Enhancement Technique for Cascode Amplifier
In this paper, a new technique is presented to increase the bandwidth for a single stage amplifier. Usually, -3 dB bandwidth of single stage amplifier is in few MHz. High output impedance and subsequent capacitive loading decrease the bandwidth of amplifier. The presented technique uses a load which itself acts as bandwidth enhancer. This high speed amplifier is designed on 180 nm CMOS technology, operates at 2.5 V power supply. This amplifier is succeeded by an output buffer to achieve a better linearity, high output swing and required output impedance for matching.
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