上扩散I2L,一种高速双极LSI工艺

D. McGreivy, B. B. Roesner
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引用次数: 7

摘要

集成注入逻辑(I2L)或合并晶体管逻辑(MTL)通常被认为是具有高封装密度的低功耗,中速逻辑技术。目前使用的标准双扩散结构不能产生许多电路所需的高速。然而,在N外延生长过程中,通过“向上扩散”埋层P基来改善NPN晶体管掺杂谱,大大提高了I2L电路的速度。此外,扇形输出和驱动能力也得到了提高,因为用这种工艺制造的晶体管的产量超过200,击穿电压为7到10伏。相比之下,标准I2L晶体管的beta值为10,击穿电压为4伏。上扩散I2L的进一步优点是易于与肖特基二极管(隔离和集电极基钳)和氧化物隔离可以合并。具有标准5微米几何形状的结隔离器件的最小栅极延迟为2.4 nsecs,典型的最小功率延迟产品小于0.2 pJ。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Up-diffused I2L, a high speed bipolar LSI process
I2L (Integrated Injection Logic) or MTL (Merged Transistor Logic) is generally considered a low power, medium speed logic technology with high packing density. The standard double diffused structures presently used cannot yield the high speeds necessary for many circuits. However, improvements in the NPN transistor doping profile by "up-diffusing" a buried layer P base during N epi growth have greatly increased the speed of I2L circuits. Also, fan out and drive capabilities are improved since transistors fabricated with this process yield betas of over 200 and breakdown voltages of 7 to 10 volts. This compares to standard I2L transistors with betas of 10 and breakdown voltages of 4 volts. Further advantages of the up-diffused I2L are the ease with which Schottky diodes (both for isolation and collector base clamps) and oxide isolation can be incorporated. Junction isolated devices with standard 5 micron geometries yield minimum gate delays of 2.4 nsecs and typical minimum power-delay products of under 0.2 pJ.
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